
Victor V. Barzykin
Examiner (ID: 16311, Phone: (571)272-0508 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2822, 2821, 2893, 2817 |
| Total Applications | 518 |
| Issued Applications | 395 |
| Pending Applications | 63 |
| Abandoned Applications | 82 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9542589
[patent_doc_number] => 20140167236
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME'
[patent_app_type] => utility
[patent_app_number] => 13/714865
[patent_app_country] => US
[patent_app_date] => 2012-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6627
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13714865
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/714865 | Integrated circuit packaging system with transferable trace lead frame | Dec 13, 2012 | Issued |
Array
(
[id] => 8884225
[patent_doc_number] => 20130157409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-20
[patent_title] => 'SELECTIVE ATOMIC LAYER DEPOSITION OF PASSIVATION LAYERS FOR SILICON-BASED PHOTOVOLTAIC DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/715767
[patent_app_country] => US
[patent_app_date] => 2012-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6012
[patent_no_of_claims] => 20
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715767
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/715767 | SELECTIVE ATOMIC LAYER DEPOSITION OF PASSIVATION LAYERS FOR SILICON-BASED PHOTOVOLTAIC DEVICES | Dec 13, 2012 | Abandoned |
Array
(
[id] => 9542580
[patent_doc_number] => 20140167227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE LAYER SETS'
[patent_app_type] => utility
[patent_app_number] => 13/714756
[patent_app_country] => US
[patent_app_date] => 2012-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13714756
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/714756 | Method of making a semiconductor device using multiple layer sets | Dec 13, 2012 | Issued |
Array
(
[id] => 11432268
[patent_doc_number] => 09570595
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-14
[patent_title] => 'Transistor and method of making'
[patent_app_type] => utility
[patent_app_number] => 13/704613
[patent_app_country] => US
[patent_app_date] => 2012-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13704613
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/704613 | Transistor and method of making | Dec 13, 2012 | Issued |
Array
(
[id] => 9546153
[patent_doc_number] => 20140170801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'METHODS OF FABRICATING A PHOTOVOLTAIC MODULE, AND RELATED SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/713697
[patent_app_country] => US
[patent_app_date] => 2012-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/713697 | Methods of fabricating a photovoltaic module, and related system | Dec 12, 2012 | Issued |
Array
(
[id] => 8863837
[patent_doc_number] => 20130147540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/690103
[patent_app_country] => US
[patent_app_date] => 2012-11-30
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/690103 | Semiconductor modules and methods of forming the same | Nov 29, 2012 | Issued |
Array
(
[id] => 9508823
[patent_doc_number] => 20140145313
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-29
[patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A BOTTOM ANTIREFLECTIVE COATING (BARC) LAYER'
[patent_app_type] => utility
[patent_app_number] => 13/686413
[patent_app_country] => US
[patent_app_date] => 2012-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 5399
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13686413
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/686413 | Method of making a semiconductor device using a bottom antireflective coating (BARC) layer | Nov 26, 2012 | Issued |
Array
(
[id] => 9446363
[patent_doc_number] => 20140117531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-01
[patent_title] => 'SEMICONDUCTOR DEVICE WITH ENCAPSULANT'
[patent_app_type] => utility
[patent_app_number] => 13/664418
[patent_app_country] => US
[patent_app_date] => 2012-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2505
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13664418
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/664418 | Semiconductor device with encapsulant | Oct 30, 2012 | Issued |
Array
(
[id] => 10151979
[patent_doc_number] => 09184277
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-10
[patent_title] => 'Super junction semiconductor device comprising a cell area and an edge area'
[patent_app_type] => utility
[patent_app_number] => 13/664924
[patent_app_country] => US
[patent_app_date] => 2012-10-31
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/664924 | Super junction semiconductor device comprising a cell area and an edge area | Oct 30, 2012 | Issued |
Array
(
[id] => 9446273
[patent_doc_number] => 20140117441
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-01
[patent_title] => 'POWER DEVICE STRUCTURES AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 13/660622
[patent_app_country] => US
[patent_app_date] => 2012-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
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[patent_no_of_words] => 5500
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660622
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/660622 | POWER DEVICE STRUCTURES AND METHODS | Oct 24, 2012 | Abandoned |
Array
(
[id] => 9418789
[patent_doc_number] => 20140103439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-17
[patent_title] => 'Transistor Device and Method for Producing a Transistor Device'
[patent_app_type] => utility
[patent_app_number] => 13/651603
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/651603 | Transistor Device and Method for Producing a Transistor Device | Oct 14, 2012 | Abandoned |
Array
(
[id] => 9394051
[patent_doc_number] => 20140091457
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-03
[patent_title] => 'CONTROLLED SOLDER HEIGHT PACKAGES AND ASSEMBLY PROCESSES'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/631939 | Controlled solder height packages and assembly processes | Sep 28, 2012 | Issued |
Array
(
[id] => 8916397
[patent_doc_number] => 20130178022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-11
[patent_title] => 'METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/618186 | METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN | Sep 13, 2012 | Abandoned |
Array
(
[id] => 9086243
[patent_doc_number] => 08557670
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-10-15
[patent_title] => 'SOI lateral bipolar junction transistor having a wide band gap emitter contact'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/605253 | SOI lateral bipolar junction transistor having a wide band gap emitter contact | Sep 5, 2012 | Issued |
Array
(
[id] => 9020272
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[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-10
[patent_title] => 'Band offset in alingap based light emitters to improve temperature performance'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/595837 | Band offset in alingap based light emitters to improve temperature performance | Aug 26, 2012 | Issued |
Array
(
[id] => 9280900
[patent_doc_number] => 20140030868
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'DEPOSIT/ETCH FOR TAPERED OXIDE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/558218 | Deposit/etch for tapered oxide | Jul 24, 2012 | Issued |
Array
(
[id] => 8637631
[patent_doc_number] => 20130029434
[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING CALIBRATING PROCESS CONDITIONS AND CONFIGURATIONS BY MONITORING PROCESSES'
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Array
(
[id] => 8617783
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/553392 | Method of manufacturing a pillar-type vertical transistor | Jul 18, 2012 | Issued |
Array
(
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[patent_title] => 'MANUFACTURING METHOD OF POWER TRANSISTOR DEVICE WITH SUPER JUNCTION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/553806 | Manufacturing method of power transistor device with super junction | Jul 18, 2012 | Issued |
Array
(
[id] => 9220279
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[patent_title] => 'FIELD EFFECT TRANSISTOR DEVICES HAVING THICK GATE DIELECTRIC LAYERS AND THIN GATE DIELECTRIC LAYERS'
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