Search

Viet Q. Nguyen

Examiner (ID: 18198, Phone: (571)272-1788 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2307, 2824, 2503, 2511, 2827, 2818
Total Applications
3921
Issued Applications
3581
Pending Applications
133
Abandoned Applications
252

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20345803 [patent_doc_number] => 12469538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Resistance change memory, memory device, and memory system [patent_app_type] => utility [patent_app_number] => 18/258405 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 4652 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18258405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/258405
Resistance change memory, memory device, and memory system Dec 15, 2021 Issued
Array ( [id] => 20345803 [patent_doc_number] => 12469538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Resistance change memory, memory device, and memory system [patent_app_type] => utility [patent_app_number] => 18/258405 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 4652 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18258405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/258405
Resistance change memory, memory device, and memory system Dec 15, 2021 Issued
Array ( [id] => 17992956 [patent_doc_number] => 20220358993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MEMORY CIRCUITS, MEMORY STRUCTURES, AND METHODS FOR FABRICATING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/643191 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643191
Memory circuits, memory structures, and methods for fabricating a memory device Dec 7, 2021 Issued
Array ( [id] => 19092883 [patent_doc_number] => 11954338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Shared components in fuse match logic [patent_app_type] => utility [patent_app_number] => 17/544407 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544407
Shared components in fuse match logic Dec 6, 2021 Issued
Array ( [id] => 18426002 [patent_doc_number] => 20230180467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => VERTICAL ACCESS LINE IN A FOLDED DIGITLINE SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/540589 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540589 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540589
Vertical access line in a folded digitline sense amplifier Dec 1, 2021 Issued
Array ( [id] => 18839969 [patent_doc_number] => 11848048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Memory device decoder configurations [patent_app_type] => utility [patent_app_number] => 17/456968 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 17459 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456968
Memory device decoder configurations Nov 29, 2021 Issued
Array ( [id] => 17477107 [patent_doc_number] => 20220084611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => ONE-TIME-PROGRAMMABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/536639 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536639
One-time-programmable memory Nov 28, 2021 Issued
Array ( [id] => 19305230 [patent_doc_number] => 20240233810 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => STORAGE DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/548035 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/548035
STORAGE DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE Nov 25, 2021 Pending
Array ( [id] => 19305230 [patent_doc_number] => 20240233810 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => STORAGE DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/548035 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/548035
STORAGE DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE Nov 25, 2021 Pending
Array ( [id] => 18396935 [patent_doc_number] => 20230165156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) WITH PRESERVED UNDERLYING DIELECTRIC LAYER [patent_app_type] => utility [patent_app_number] => 17/534485 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534485
Magnetoresistive random-access memory (MRAM) with preserved underlying dielectric layer Nov 23, 2021 Issued
Array ( [id] => 18578706 [patent_doc_number] => 11735245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-22 [patent_title] => Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects [patent_app_type] => utility [patent_app_number] => 17/532552 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532552
Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects Nov 21, 2021 Issued
Array ( [id] => 18645465 [patent_doc_number] => 11769543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-26 [patent_title] => Writing scheme for 1TNC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/532556 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532556
Writing scheme for 1TNC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell Nov 21, 2021 Issued
Array ( [id] => 18766733 [patent_doc_number] => 11817140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-14 [patent_title] => Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/532647 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532647
Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell Nov 21, 2021 Issued
Array ( [id] => 18704456 [patent_doc_number] => 11790972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/532652 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532652
Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell Nov 21, 2021 Issued
Array ( [id] => 18480986 [patent_doc_number] => 11694737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-04 [patent_title] => Write scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize write disturb effects [patent_app_type] => utility [patent_app_number] => 17/532545 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532545
Write scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize write disturb effects Nov 21, 2021 Issued
Array ( [id] => 18357665 [patent_doc_number] => 11646071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-09 [patent_title] => Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/532657 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532657
Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell Nov 21, 2021 Issued
Array ( [id] => 18401916 [patent_doc_number] => 11664060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-30 [patent_title] => Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/531535 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531535
Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell Nov 18, 2021 Issued
Array ( [id] => 18248817 [patent_doc_number] => 11605413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/531577 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531577 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531577
Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell Nov 18, 2021 Issued
Array ( [id] => 18073507 [patent_doc_number] => 11532344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-20 [patent_title] => Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/530366 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530366
Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell Nov 17, 2021 Issued
Array ( [id] => 18507384 [patent_doc_number] => 11705208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Read level calibration in memory devices using embedded servo cells [patent_app_type] => utility [patent_app_number] => 17/530368 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6438 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530368
Read level calibration in memory devices using embedded servo cells Nov 17, 2021 Issued
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