Search

Viet Q. Nguyen

Examiner (ID: 10659, Phone: (571)272-1788 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2307, 2503, 2511, 2818, 2827, 2824
Total Applications
3976
Issued Applications
3621
Pending Applications
133
Abandoned Applications
252

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19559641 [patent_doc_number] => 20240371433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => MEMORY CIRCUITS, MEMORY STRUCTURES, AND METHODS FOR FABRICATING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/772117 [patent_app_country] => US [patent_app_date] => 2024-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772117
Memory circuits, memory structures, and methods for fabricating a memory device Jul 12, 2024 Issued
Array ( [id] => 20732954 [patent_doc_number] => 12640214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Access line voltage ramp rate adjustment [patent_app_type] => utility [patent_app_number] => 18/771479 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771479
Access line voltage ramp rate adjustment Jul 11, 2024 Issued
Array ( [id] => 19546126 [patent_doc_number] => 20240363162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Methods for Reading Resistive States of Resistive Change Elements [patent_app_type] => utility [patent_app_number] => 18/770397 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 75208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770397
Methods for Reading Resistive States of Resistive Change Elements Jul 10, 2024 Abandoned
Array ( [id] => 20002100 [patent_doc_number] => 20250140322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING BY CREATING A PSEUDO PN JUNCTION [patent_app_type] => utility [patent_app_number] => 18/768974 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768974
Selectively erasing one of multiple erase blocks coupled to a same string by creating a pseudo PN junction Jul 9, 2024 Issued
Array ( [id] => 19531486 [patent_doc_number] => 20240355388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MEMORY CELL INCLUDING PROGRAMMABLE RESISTORS WITH TRANSISTOR COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/758901 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758901 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758901
Memory cell including programmable resistors with transistor components Jun 27, 2024 Issued
Array ( [id] => 20448105 [patent_doc_number] => 20260004829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MEMORY CIRCUIT WITH BIT LINE CLAMPS [patent_app_type] => utility [patent_app_number] => 18/758730 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758730
MEMORY CIRCUIT WITH BIT LINE CLAMPS Jun 27, 2024 Pending
Array ( [id] => 20448102 [patent_doc_number] => 20260004826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MEMORY WITH REDUNDANT READ OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/757302 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757302 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757302
Memory with redundant read optimization Jun 26, 2024 Issued
Array ( [id] => 20718114 [patent_doc_number] => 12633370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Repairing defective columns of compute-in-memory and near-memory computing devices [patent_app_type] => utility [patent_app_number] => 18/755329 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755329 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/755329
Repairing defective columns of compute-in-memory and near-memory computing devices Jun 25, 2024 Issued
Array ( [id] => 19893046 [patent_doc_number] => 20250118358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/746339 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746339
Apparatuses and methods for single and multi memory cell architectures Jun 17, 2024 Issued
Array ( [id] => 19820704 [patent_doc_number] => 20250078911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/745943 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745943 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745943
METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND MEMORY DEVICES Jun 16, 2024 Pending
Array ( [id] => 20581210 [patent_doc_number] => 12573464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Memory controller useable for a dynamic random access memory (DRAM) health monitor [patent_app_type] => utility [patent_app_number] => 18/736883 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18736883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/736883
Memory controller useable for a dynamic random access memory (DRAM) health monitor Jun 6, 2024 Issued
Array ( [id] => 19467696 [patent_doc_number] => 20240321366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE, AND OPERATING METHOD OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/734833 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734833
NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE, AND OPERATING METHOD OF STORAGE DEVICE Jun 4, 2024 Pending
Array ( [id] => 20495179 [patent_doc_number] => 12537055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/731731 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731731
Semiconductor device Jun 2, 2024 Issued
Array ( [id] => 20806041 [patent_doc_number] => 12670953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Sense amplifier circuit, corresponding memory device and method of operation [patent_app_type] => utility [patent_app_number] => 18/676630 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1108 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676630
Sense amplifier circuit, corresponding memory device and method of operation May 28, 2024 Issued
Array ( [id] => 19450926 [patent_doc_number] => 20240311056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORY CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/677655 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677655 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677655
Memory controller and operating method thereof May 28, 2024 Issued
Array ( [id] => 20831520 [patent_doc_number] => 12685124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Memory array circuit [patent_app_type] => utility [patent_app_number] => 18/673345 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 5602 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673345
Memory array circuit May 23, 2024 Issued
Array ( [id] => 20455781 [patent_doc_number] => 12518841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => One-time-programmable memory [patent_app_type] => utility [patent_app_number] => 18/672623 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672623
One-time-programmable memory May 22, 2024 Issued
Array ( [id] => 19604430 [patent_doc_number] => 20240395310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SIGNAL SKEW IN SOURCE-SYNCHRONOUS SYSTEM [patent_app_type] => utility [patent_app_number] => 18/673246 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673246
Signal skew in source-synchronous system May 22, 2024 Issued
Array ( [id] => 19604409 [patent_doc_number] => 20240395289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => LOGIC DIE-BASED TECHNIQUES FOR DRAM ROW SEGMENTATION AND FINE-GRAINED ACCESSES ON STACKED MEMORY [patent_app_type] => utility [patent_app_number] => 18/671854 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671854
LOGIC DIE-BASED TECHNIQUES FOR DRAM ROW SEGMENTATION AND FINE-GRAINED ACCESSES ON STACKED MEMORY May 21, 2024 Pending
Array ( [id] => 20790170 [patent_doc_number] => 12664085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Triggering non-target on-die termination on a memory device [patent_app_type] => utility [patent_app_number] => 18/669824 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669824
Triggering non-target on-die termination on a memory device May 20, 2024 Issued
Menu