Viet Q. Nguyen

Array ( [id] => 19235903 [patent_doc_number] => 20240193098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE [patent_app_type] => utility [patent_app_number] => 18/442660 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 95400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20375064 [patent_doc_number] => 12482506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Magnon junction, magnon random access memory, magnon microwave oscillator and detector, electronic device [patent_app_type] => utility [patent_app_number] => 18/440928 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3309 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20063057 [patent_doc_number] => 20250201279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SYSTEM AND METHOD FOR IMPROVING SAFETY OF INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/435286 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20286396 [patent_doc_number] => 20250311638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SCALABLE SPINTRONIC DEVICES FORMED ON SILICON WAFERS [patent_app_type] => utility [patent_app_number] => 18/435084 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20139171 [patent_doc_number] => 20250246215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => INTEGRATION OF MEMORY CELLS AND LOGIC CELLS FOR COMPUTE-IN-MEMORY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/427079 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19321212 [patent_doc_number] => 20240242758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => MEMORY ARRAY WITH MULTIPLEXED DIGIT LINES [patent_app_type] => utility [patent_app_number] => 18/421741 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19993739 [patent_doc_number] => 20250131961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/419557 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19321204 [patent_doc_number] => 20240242750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => FERROELECTRIC FET-BASED CONTENT-ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 18/420171 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20611052 [patent_doc_number] => 12586657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Nonvolatile memory with temperature-dependent sense time offsets for soft-bit read [patent_app_type] => utility [patent_app_number] => 18/415703 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 7260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19160834 [patent_doc_number] => 20240153541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Integrated Assemblies and Methods Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 18/413671 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20332866 [patent_doc_number] => 12463151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => PUF memory devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 18/405926 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 11409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20551412 [patent_doc_number] => 12562210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Voltage supply circuit, memory device including the same, and operating method of memory device [patent_app_type] => utility [patent_app_number] => 18/404411 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20036044 [patent_doc_number] => 20250174266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => DECODER CIRCUITS, MEMORY DEVICES AND ITS CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/392745 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18392745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20071879 [patent_doc_number] => 20250210101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => MICROELECTRONIC DEVICES AND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/393416 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20230367 [patent_doc_number] => 12419032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Memory device including semiconductor element [patent_app_type] => utility [patent_app_number] => 18/545163 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 3925 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19100766 [patent_doc_number] => 20240119994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => VERTICAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/542769 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18542769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19237051 [patent_doc_number] => 20240194246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => METHOD FOR CONTROLLING NAND FLASH MEMORY TO IMPLEMENT XNOR OPERATION [patent_app_type] => utility [patent_app_number] => 18/534834 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 654 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20469261 [patent_doc_number] => 12525303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/531872 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18531872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19285367 [patent_doc_number] => 20240221844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/532730 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18532730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19070842 [patent_doc_number] => 20240105268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/529897 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529897 [rel_patent_id] =>[rel_patent_doc_number] =>)