Search

Viet Q. Nguyen

Examiner (ID: 18198, Phone: (571)272-1788 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2307, 2824, 2503, 2511, 2827, 2818
Total Applications
3921
Issued Applications
3581
Pending Applications
133
Abandoned Applications
252

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20111271 [patent_doc_number] => 12362006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor-element-including memory device [patent_app_type] => utility [patent_app_number] => 18/333674 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4723 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333674
Semiconductor-element-including memory device Jun 12, 2023 Issued
Array ( [id] => 20111270 [patent_doc_number] => 12362005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/331328 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2564 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331328
Semiconductor memory device Jun 7, 2023 Issued
Array ( [id] => 19168241 [patent_doc_number] => 11984152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Memory device and electronic device [patent_app_type] => utility [patent_app_number] => 18/206117 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 77 [patent_no_of_words] => 40353 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206117
Memory device and electronic device Jun 5, 2023 Issued
Array ( [id] => 18663262 [patent_doc_number] => 20230309288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR ELEMENT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/326709 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326709 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326709
Semiconductor element memory device May 30, 2023 Issued
Array ( [id] => 20345831 [patent_doc_number] => 12469566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Memory device performing read operation and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/325730 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 1161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325730
Memory device performing read operation and method of operating the same May 29, 2023 Issued
Array ( [id] => 19628825 [patent_doc_number] => 12167703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Electronic chip with two phase change memories [patent_app_type] => utility [patent_app_number] => 18/321347 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 9040 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321347
Electronic chip with two phase change memories May 21, 2023 Issued
Array ( [id] => 19589386 [patent_doc_number] => 20240386943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SCALED 2T DRAM [patent_app_type] => utility [patent_app_number] => 18/320234 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320234 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320234
Scaled 2T DRAM May 18, 2023 Issued
Array ( [id] => 19875110 [patent_doc_number] => 12267996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => DRAM sense amplifier architecture with reduced power consumption and related methods [patent_app_type] => utility [patent_app_number] => 18/311465 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 9534 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311465 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311465
DRAM sense amplifier architecture with reduced power consumption and related methods May 2, 2023 Issued
Array ( [id] => 19452819 [patent_doc_number] => 20240312949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => LAYOUT STRUCTURE OF DIFFERENTIAL LINES, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/306971 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306971
Layout structure of differential lines, memory storage device and memory control circuit unit Apr 24, 2023 Issued
Array ( [id] => 19452819 [patent_doc_number] => 20240312949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => LAYOUT STRUCTURE OF DIFFERENTIAL LINES, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/306971 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306971
Layout structure of differential lines, memory storage device and memory control circuit unit Apr 24, 2023 Issued
Array ( [id] => 19452819 [patent_doc_number] => 20240312949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => LAYOUT STRUCTURE OF DIFFERENTIAL LINES, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/306971 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306971
Layout structure of differential lines, memory storage device and memory control circuit unit Apr 24, 2023 Issued
Array ( [id] => 19079271 [patent_doc_number] => 11948646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/305654 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 25362 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305654 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305654
Semiconductor memory Apr 23, 2023 Issued
Array ( [id] => 18815112 [patent_doc_number] => 20230389450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => PHASE-CHANGE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/305268 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305268 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305268
Phase-change memory cell Apr 20, 2023 Issued
Array ( [id] => 19454887 [patent_doc_number] => 20240315017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => RESISTOR BETWEEN DUMMY FLASH STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/135712 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135712
RESISTOR BETWEEN DUMMY FLASH STRUCTURES Apr 16, 2023 Pending
Array ( [id] => 18555024 [patent_doc_number] => 20230253040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => MEMORY CELL INCLUDING PROGRAMMABLE RESISTORS WITH TRANSISTOR COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/301745 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301745 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301745
Memory cell including programmable resistors with transistor components Apr 16, 2023 Issued
Array ( [id] => 19378250 [patent_doc_number] => 12069847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Thin film transistor deck selection in a memory device [patent_app_type] => utility [patent_app_number] => 18/133929 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 24268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18133929 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/133929
Thin film transistor deck selection in a memory device Apr 11, 2023 Issued
Array ( [id] => 19384302 [patent_doc_number] => 20240274172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY PACKAGE, STORAGE DEVICE INCLUDING MEMORY PACKAGE, AND STORAGE DEVICE OPERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/133247 [patent_app_country] => US [patent_app_date] => 2023-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18133247 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/133247
Memory package, storage device including memory package, and storage device operating method Apr 10, 2023 Issued
Array ( [id] => 18663261 [patent_doc_number] => 20230309287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/187764 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18187764 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/187764
Semiconductor memory device Mar 21, 2023 Issued
Array ( [id] => 19392477 [patent_doc_number] => 20240282347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHOD FOR CONTROLLING TEMPERATURE OF CHIPS AND RELATED CHIPS [patent_app_type] => utility [patent_app_number] => 18/185127 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18185127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/185127
Method for controlling temperature of chips and related chips Mar 15, 2023 Issued
Array ( [id] => 20080596 [patent_doc_number] => 12354671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/184893 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 77 [patent_no_of_words] => 45385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184893 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184893
Semiconductor memory device Mar 15, 2023 Issued
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