Search

Viet Q. Nguyen

Examiner (ID: 18198, Phone: (571)272-1788 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2307, 2824, 2503, 2511, 2827, 2818
Total Applications
3921
Issued Applications
3581
Pending Applications
133
Abandoned Applications
252

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19392477 [patent_doc_number] => 20240282347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHOD FOR CONTROLLING TEMPERATURE OF CHIPS AND RELATED CHIPS [patent_app_type] => utility [patent_app_number] => 18/185127 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18185127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/185127
Method for controlling temperature of chips and related chips Mar 15, 2023 Issued
Array ( [id] => 20080596 [patent_doc_number] => 12354671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/184893 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 77 [patent_no_of_words] => 45385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184893 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184893
Semiconductor memory device Mar 15, 2023 Issued
Array ( [id] => 19906294 [patent_doc_number] => 12283306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Memory device including semiconductor [patent_app_type] => utility [patent_app_number] => 18/184309 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 1182 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184309 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184309
Memory device including semiconductor Mar 14, 2023 Issued
Array ( [id] => 18615529 [patent_doc_number] => 20230282266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => PROTOCOL FOR MEMORY POWER-MODE CONTROL [patent_app_type] => utility [patent_app_number] => 18/181185 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181185 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/181185
Protocol for memory power-mode control Mar 8, 2023 Issued
Array ( [id] => 18974945 [patent_doc_number] => 20240055037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => PSEUDO-STATIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/179205 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/179205
Pseudo-static random access memory Mar 5, 2023 Issued
Array ( [id] => 19420751 [patent_doc_number] => 20240296875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MULTI-VOLTAGE RAM USED TO CROSS CLOCK AND VOLTAGE DOMAINS [patent_app_type] => utility [patent_app_number] => 18/176836 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176836
Multi-voltage RAM used to cross clock and voltage domains Feb 28, 2023 Issued
Array ( [id] => 18458985 [patent_doc_number] => 20230200267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => MULTI-LAYER PHASE CHANGE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/172385 [patent_app_country] => US [patent_app_date] => 2023-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172385 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/172385
Multi-layer phase change memory device Feb 21, 2023 Issued
Array ( [id] => 20111250 [patent_doc_number] => 12361985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/170109 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170109
Memory device Feb 15, 2023 Issued
Array ( [id] => 20111250 [patent_doc_number] => 12361985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/170109 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170109
Memory device Feb 15, 2023 Issued
Array ( [id] => 18615556 [patent_doc_number] => 20230282293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => DETERMINING VOLTAGE OFFSETS FOR MEMORY READ OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/110008 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110008
Determining voltage offsets for memory read operations Feb 14, 2023 Issued
Array ( [id] => 20118212 [patent_doc_number] => 12367927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Pseudo-differential de-glitch sense amplifier [patent_app_type] => utility [patent_app_number] => 18/104167 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2546 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104167
Pseudo-differential de-glitch sense amplifier Jan 30, 2023 Issued
Array ( [id] => 18424074 [patent_doc_number] => 20230178538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => TSV Coupled Integrated Circuits and Methods [patent_app_type] => utility [patent_app_number] => 18/103313 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103313
TSV Coupled Integrated Circuits and Methods Jan 29, 2023 Pending
Array ( [id] => 18424074 [patent_doc_number] => 20230178538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => TSV Coupled Integrated Circuits and Methods [patent_app_type] => utility [patent_app_number] => 18/103313 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103313
TSV Coupled Integrated Circuits and Methods Jan 29, 2023 Pending
Array ( [id] => 18424074 [patent_doc_number] => 20230178538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => TSV Coupled Integrated Circuits and Methods [patent_app_type] => utility [patent_app_number] => 18/103313 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103313
TSV Coupled Integrated Circuits and Methods Jan 29, 2023 Pending
Array ( [id] => 19351297 [patent_doc_number] => 20240260261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Multi-Stack Bitcell Architecture [patent_app_type] => utility [patent_app_number] => 18/103316 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103316
Multi-Stack Bitcell Architecture Jan 29, 2023 Pending
Array ( [id] => 19351297 [patent_doc_number] => 20240260261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Multi-Stack Bitcell Architecture [patent_app_type] => utility [patent_app_number] => 18/103316 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103316
Multi-Stack Bitcell Architecture Jan 29, 2023 Pending
Array ( [id] => 18848513 [patent_doc_number] => 20230410917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => NONVOLATILE MEMORY DEVICE INCLUDING POWER GATING CIRCUIT AND INPUT/OUTPUT CIRCUIT OF A NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/100173 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100173 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100173
Nonvolatile memory device including power gating circuit and input/output circuit of a nonvolatile memory device Jan 22, 2023 Issued
Array ( [id] => 19720121 [patent_doc_number] => 12205664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Memory circuit and method of operating same [patent_app_type] => utility [patent_app_number] => 18/157240 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157240 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157240
Memory circuit and method of operating same Jan 19, 2023 Issued
Array ( [id] => 20161136 [patent_doc_number] => 12387769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Latency adjustment method, memory chip architecture, and semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/156461 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1196 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156461 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156461
Latency adjustment method, memory chip architecture, and semiconductor memory Jan 18, 2023 Issued
Array ( [id] => 20161136 [patent_doc_number] => 12387769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Latency adjustment method, memory chip architecture, and semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/156461 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1196 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156461 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156461
Latency adjustment method, memory chip architecture, and semiconductor memory Jan 18, 2023 Issued
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