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Viktor Simkovic

Examiner (ID: 10258)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
255
Issued Applications
216
Pending Applications
18
Abandoned Applications
21

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2949128 [patent_doc_number] => 05247693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Computer language structure for process control applications and method of translating same into program code to operate the computer' [patent_app_type] => 1 [patent_app_number] => 7/978180 [patent_app_country] => US [patent_app_date] => 1992-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 37 [patent_no_of_words] => 11883 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247693.pdf [firstpage_image] =>[orig_patent_app_number] => 978180 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/978180
Computer language structure for process control applications and method of translating same into program code to operate the computer Nov 16, 1992 Issued
07/976127 PERSONAL COMMUNICATOR APPARATUS Nov 12, 1992 Abandoned
07/963753 COOPERATIVE DISTRIBUTED PROBLEM SOLVER Oct 19, 1992 Abandoned
Array ( [id] => 3501966 [patent_doc_number] => 05471629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Method of monitoring changes in an object-oriented database with tuned monitors' [patent_app_type] => 1 [patent_app_number] => 7/918182 [patent_app_country] => US [patent_app_date] => 1992-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 11132 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471629.pdf [firstpage_image] =>[orig_patent_app_number] => 918182 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/918182
Method of monitoring changes in an object-oriented database with tuned monitors Jul 19, 1992 Issued
07/914353 MULTIPROCESSOR SYSTEM HAVING RESPECTIVE BUS INTERFACES THAT TRANSFER DATA AT THE SAME TIME Jul 16, 1992 Abandoned
07/913358 PARALLEL PROCESSOR SYSTEM PROVIDING MEANS FOR DETECTING THE END OF DATA TRANSMISSION Jul 14, 1992 Abandoned
Array ( [id] => 3041940 [patent_doc_number] => 05349686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Method and circuit for programmably selecting a variable sequence of elements using write-back' [patent_app_type] => 1 [patent_app_number] => 7/913104 [patent_app_country] => US [patent_app_date] => 1992-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4865 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349686.pdf [firstpage_image] =>[orig_patent_app_number] => 913104 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/913104
Method and circuit for programmably selecting a variable sequence of elements using write-back Jul 13, 1992 Issued
Array ( [id] => 2949109 [patent_doc_number] => 05247692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Multiple file system having a plurality of file units holding the same files in which loss of data is prevented in a failure of a file unit' [patent_app_type] => 1 [patent_app_number] => 7/911789 [patent_app_country] => US [patent_app_date] => 1992-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2352 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247692.pdf [firstpage_image] =>[orig_patent_app_number] => 911789 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/911789
Multiple file system having a plurality of file units holding the same files in which loss of data is prevented in a failure of a file unit Jul 9, 1992 Issued
07/907551 A HIERARCHICAL STRUCTURE PROCESSOR HAVING AT LEAST ONE SUB-SEQUENCER FOR EXECUTING BASIC INSTRUCTIONS OF A MACRO INSTRUCTION Jul 1, 1992 Abandoned
Array ( [id] => 2902242 [patent_doc_number] => 05239662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'System including multiple device communications controller which coverts data received from two different customer transaction devices each using different communications protocols into a single communications protocol' [patent_app_type] => 1 [patent_app_number] => 7/905000 [patent_app_country] => US [patent_app_date] => 1992-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 19 [patent_no_of_words] => 5932 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239662.pdf [firstpage_image] =>[orig_patent_app_number] => 905000 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/905000
System including multiple device communications controller which coverts data received from two different customer transaction devices each using different communications protocols into a single communications protocol Jun 25, 1992 Issued
Array ( [id] => 2934218 [patent_doc_number] => 05201052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'System for transferring first and second ring information from program status word register and store buffer' [patent_app_type] => 1 [patent_app_number] => 7/899946 [patent_app_country] => US [patent_app_date] => 1992-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4378 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/201/05201052.pdf [firstpage_image] =>[orig_patent_app_number] => 899946 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/899946
System for transferring first and second ring information from program status word register and store buffer Jun 16, 1992 Issued
07/889551 APPARATUS AND METHOD FOR CONTROLLING PACKET AGE IN COMPUTER NETWORKS May 26, 1992 Abandoned
Array ( [id] => 3434072 [patent_doc_number] => 05390355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions' [patent_app_type] => 1 [patent_app_number] => 7/890299 [patent_app_country] => US [patent_app_date] => 1992-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 7397 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390355.pdf [firstpage_image] =>[orig_patent_app_number] => 890299 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/890299
Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions May 26, 1992 Issued
07/887997 ARRAY PROCESSOR DOTTED COMMUNICATION NETWORK BASED ON H-DOTS May 21, 1992 Abandoned
Array ( [id] => 3128307 [patent_doc_number] => 05396640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Boosting method and apparatus in a parallel computer' [patent_app_type] => 1 [patent_app_number] => 7/883948 [patent_app_country] => US [patent_app_date] => 1992-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 6613 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396640.pdf [firstpage_image] =>[orig_patent_app_number] => 883948 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/883948
Boosting method and apparatus in a parallel computer May 14, 1992 Issued
Array ( [id] => 3626992 [patent_doc_number] => 05535402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'System for (N.cndot.M)-bit correlation using N M-bit correlators' [patent_app_type] => 1 [patent_app_number] => 7/876151 [patent_app_country] => US [patent_app_date] => 1992-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535402.pdf [firstpage_image] =>[orig_patent_app_number] => 876151 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/876151
System for (N.cndot.M)-bit correlation using N M-bit correlators Apr 29, 1992 Issued
Array ( [id] => 2934256 [patent_doc_number] => 05201054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Apparatus and method for controlling the transfer of digital information between service processors memories in a computer' [patent_app_type] => 1 [patent_app_number] => 7/870781 [patent_app_country] => US [patent_app_date] => 1992-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7156 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 416 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/201/05201054.pdf [firstpage_image] =>[orig_patent_app_number] => 870781 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/870781
Apparatus and method for controlling the transfer of digital information between service processors memories in a computer Apr 15, 1992 Issued
Array ( [id] => 3473798 [patent_doc_number] => 05392443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data' [patent_app_type] => 1 [patent_app_number] => 7/855056 [patent_app_country] => US [patent_app_date] => 1992-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 42 [patent_no_of_words] => 16351 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392443.pdf [firstpage_image] =>[orig_patent_app_number] => 855056 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/855056
Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data Mar 18, 1992 Issued
Array ( [id] => 3456448 [patent_doc_number] => 05388220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Parallel processing system and data transfer method which reduces bus contention by use of data relays having plurality of buffers' [patent_app_type] => 1 [patent_app_number] => 7/853249 [patent_app_country] => US [patent_app_date] => 1992-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 6906 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388220.pdf [firstpage_image] =>[orig_patent_app_number] => 853249 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/853249
Parallel processing system and data transfer method which reduces bus contention by use of data relays having plurality of buffers Mar 17, 1992 Issued
Array ( [id] => 3745280 [patent_doc_number] => 05694572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Controllably operable method and apparatus for predicting addresses of future operand requests by examination of addresses of prior cache misses' [patent_app_type] => 1 [patent_app_number] => 7/841687 [patent_app_country] => US [patent_app_date] => 1992-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4415 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694572.pdf [firstpage_image] =>[orig_patent_app_number] => 841687 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/841687
Controllably operable method and apparatus for predicting addresses of future operand requests by examination of addresses of prior cache misses Feb 25, 1992 Issued
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