
Viktor Simkovic
Examiner (ID: 10581)
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 255 |
| Issued Applications | 216 |
| Pending Applications | 18 |
| Abandoned Applications | 21 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4257893
[patent_doc_number] => 06204098
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Method of formation in a silicon wafer of an insulated well'
[patent_app_type] => 1
[patent_app_number] => 9/426221
[patent_app_country] => US
[patent_app_date] => 1999-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 19
[patent_no_of_words] => 3200
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/204/06204098.pdf
[firstpage_image] =>[orig_patent_app_number] => 426221
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/426221 | Method of formation in a silicon wafer of an insulated well | Oct 21, 1999 | Issued |
Array
(
[id] => 1297433
[patent_doc_number] => 06627518
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Method for making three-dimensional device'
[patent_app_type] => B1
[patent_app_number] => 09/403342
[patent_app_country] => US
[patent_app_date] => 1999-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/627/06627518.pdf
[firstpage_image] =>[orig_patent_app_number] => 09403342
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/403342 | Method for making three-dimensional device | Oct 17, 1999 | Issued |
Array
(
[id] => 4302292
[patent_doc_number] => 06187616
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Method for fabricating semiconductor device and heat treatment apparatus'
[patent_app_type] => 1
[patent_app_number] => 9/402891
[patent_app_country] => US
[patent_app_date] => 1999-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 11045
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/187/06187616.pdf
[firstpage_image] =>[orig_patent_app_number] => 402891
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/402891 | Method for fabricating semiconductor device and heat treatment apparatus | Oct 12, 1999 | Issued |
Array
(
[id] => 4378092
[patent_doc_number] => 06303471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Method of manufacturing semiconductor device having reinforcing member and method of manufacturing IC card using the device'
[patent_app_type] => 1
[patent_app_number] => 9/416820
[patent_app_country] => US
[patent_app_date] => 1999-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 17
[patent_no_of_words] => 4554
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[patent_words_short_claim] => 139
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/303/06303471.pdf
[firstpage_image] =>[orig_patent_app_number] => 416820
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/416820 | Method of manufacturing semiconductor device having reinforcing member and method of manufacturing IC card using the device | Oct 11, 1999 | Issued |
Array
(
[id] => 4257516
[patent_doc_number] => 06204071
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Method of fabrication of striped magnetoresistive (SMR) and dual stripe magnetoresistive (DSMR) heads with anti-parallel exchange configuration'
[patent_app_type] => 1
[patent_app_number] => 9/408491
[patent_app_country] => US
[patent_app_date] => 1999-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3089
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/204/06204071.pdf
[firstpage_image] =>[orig_patent_app_number] => 408491
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/408491 | Method of fabrication of striped magnetoresistive (SMR) and dual stripe magnetoresistive (DSMR) heads with anti-parallel exchange configuration | Sep 29, 1999 | Issued |
Array
(
[id] => 4258327
[patent_doc_number] => 06258631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Semiconductor package and the manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/408024
[patent_app_country] => US
[patent_app_date] => 1999-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3923
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[pdf_file] => patents/06/258/06258631.pdf
[firstpage_image] =>[orig_patent_app_number] => 408024
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/408024 | Semiconductor package and the manufacturing method | Sep 28, 1999 | Issued |
Array
(
[id] => 4354216
[patent_doc_number] => 06200835
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-13
[patent_title] => 'Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors'
[patent_app_type] => 1
[patent_app_number] => 9/406201
[patent_app_country] => US
[patent_app_date] => 1999-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 2529
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/200/06200835.pdf
[firstpage_image] =>[orig_patent_app_number] => 406201
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/406201 | Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors | Sep 26, 1999 | Issued |
Array
(
[id] => 1532399
[patent_doc_number] => 06410374
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Method of crystallizing a semiconductor layer in a MIS transistor'
[patent_app_type] => B1
[patent_app_number] => 09/409662
[patent_app_country] => US
[patent_app_date] => 1999-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 42
[patent_no_of_words] => 5447
[patent_no_of_claims] => 58
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[pdf_file] => patents/06/410/06410374.pdf
[firstpage_image] =>[orig_patent_app_number] => 09409662
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/409662 | Method of crystallizing a semiconductor layer in a MIS transistor | Sep 19, 1999 | Issued |
Array
(
[id] => 4235779
[patent_doc_number] => 06143629
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Process for producing semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 9/389361
[patent_app_country] => US
[patent_app_date] => 1999-09-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/143/06143629.pdf
[firstpage_image] =>[orig_patent_app_number] => 389361
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/389361 | Process for producing semiconductor substrate | Sep 2, 1999 | Issued |
Array
(
[id] => 1440977
[patent_doc_number] => 06335231
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-01
[patent_title] => 'Method of fabricating a high reliable SOI substrate'
[patent_app_type] => B1
[patent_app_number] => 09/386782
[patent_app_country] => US
[patent_app_date] => 1999-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 7791
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[pdf_file] => patents/06/335/06335231.pdf
[firstpage_image] =>[orig_patent_app_number] => 09386782
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/386782 | Method of fabricating a high reliable SOI substrate | Aug 30, 1999 | Issued |
Array
(
[id] => 4086653
[patent_doc_number] => 06133076
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Manufacturing method of semiconductor'
[patent_app_type] => 1
[patent_app_number] => 9/379981
[patent_app_country] => US
[patent_app_date] => 1999-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 7870
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[pdf_file] => patents/06/133/06133076.pdf
[firstpage_image] =>[orig_patent_app_number] => 379981
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/379981 | Manufacturing method of semiconductor | Aug 23, 1999 | Issued |
Array
(
[id] => 4269282
[patent_doc_number] => 06245590
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-12
[patent_title] => 'Frequency tunable resonant scanner and method of making'
[patent_app_type] => 1
[patent_app_number] => 9/369674
[patent_app_country] => US
[patent_app_date] => 1999-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
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[pdf_file] => patents/06/245/06245590.pdf
[firstpage_image] =>[orig_patent_app_number] => 369674
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/369674 | Frequency tunable resonant scanner and method of making | Aug 4, 1999 | Issued |
Array
(
[id] => 4246043
[patent_doc_number] => 06136667
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Method for bonding two crystalline substrates together'
[patent_app_type] => 1
[patent_app_number] => 9/369682
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[pdf_file] => patents/06/136/06136667.pdf
[firstpage_image] =>[orig_patent_app_number] => 369682
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/369682 | Method for bonding two crystalline substrates together | Aug 4, 1999 | Issued |
Array
(
[id] => 4168517
[patent_doc_number] => 06140146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Automated RFID transponder manufacturing on flexible tape substrates'
[patent_app_type] => 1
[patent_app_number] => 9/365792
[patent_app_country] => US
[patent_app_date] => 1999-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/140/06140146.pdf
[firstpage_image] =>[orig_patent_app_number] => 365792
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/365792 | Automated RFID transponder manufacturing on flexible tape substrates | Aug 2, 1999 | Issued |
Array
(
[id] => 4145756
[patent_doc_number] => 06063678
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Fabrication of lateral RF MOS devices with enhanced RF properties'
[patent_app_type] => 1
[patent_app_number] => 9/366612
[patent_app_country] => US
[patent_app_date] => 1999-07-31
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[pdf_file] => patents/06/063/06063678.pdf
[firstpage_image] =>[orig_patent_app_number] => 366612
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/366612 | Fabrication of lateral RF MOS devices with enhanced RF properties | Jul 30, 1999 | Issued |
Array
(
[id] => 4271386
[patent_doc_number] => 06323108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Fabrication ultra-thin bonded semiconductor layers'
[patent_app_type] => 1
[patent_app_number] => 9/373031
[patent_app_country] => US
[patent_app_date] => 1999-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/323/06323108.pdf
[firstpage_image] =>[orig_patent_app_number] => 373031
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373031 | Fabrication ultra-thin bonded semiconductor layers | Jul 26, 1999 | Issued |
| 09/360342 | SUBSTRATE SENSOR | Jul 21, 1999 | Abandoned |
Array
(
[id] => 4214218
[patent_doc_number] => 06110766
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Methods of fabricating aluminum gates by implanting ions to form composite layers'
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[patent_app_number] => 9/352071
[patent_app_country] => US
[patent_app_date] => 1999-07-14
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[pdf_file] => patents/06/110/06110766.pdf
[firstpage_image] =>[orig_patent_app_number] => 352071
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/352071 | Methods of fabricating aluminum gates by implanting ions to form composite layers | Jul 13, 1999 | Issued |
Array
(
[id] => 4130732
[patent_doc_number] => 06146929
[patent_country] => US
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[patent_issue_date] => 2000-11-14
[patent_title] => 'Method for manufacturing semiconductor device using multiple steps continuously without exposing substrate to the atmosphere'
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[pdf_file] => patents/06/146/06146929.pdf
[firstpage_image] =>[orig_patent_app_number] => 347862
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/347862 | Method for manufacturing semiconductor device using multiple steps continuously without exposing substrate to the atmosphere | Jul 8, 1999 | Issued |
Array
(
[id] => 4344420
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[patent_issue_date] => 2001-09-04
[patent_title] => 'Method of fabricating an SOI wafer and SOI wafer fabricated by the method'
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[firstpage_image] =>[orig_patent_app_number] => 343074
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/343074 | Method of fabricating an SOI wafer and SOI wafer fabricated by the method | Jun 28, 1999 | Issued |