Search

Vincent N. Trans

Examiner (ID: 12114)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2787, 2899, OPET
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
16/350388 CONTINUOUS POWER SUPPLY FOR ELECTRIC VEHICLES Oct 29, 2017 Abandoned
Array ( [id] => 14070407 [patent_doc_number] => 20190084091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Real Time Monitoring Method and Process Control for Water Jet Guided Laser System Machining [patent_app_type] => utility [patent_app_number] => 15/998241 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15998241 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/998241
Real Time Monitoring Method and Process Control for Water Jet Guided Laser System Machining May 30, 2017 Abandoned
Array ( [id] => 3820671 [patent_doc_number] => 05831868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Test ready compiler for design for test synthesis' [patent_app_type] => 1 [patent_app_number] => 8/987868 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 15959 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831868.pdf [firstpage_image] =>[orig_patent_app_number] => 987868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987868
Test ready compiler for design for test synthesis Dec 8, 1997 Issued
Array ( [id] => 3896058 [patent_doc_number] => 05894420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Method for spawning two independent states in a state flow diagram' [patent_app_type] => 1 [patent_app_number] => 8/970344 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 69 [patent_no_of_words] => 21577 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894420.pdf [firstpage_image] =>[orig_patent_app_number] => 970344 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970344
Method for spawning two independent states in a state flow diagram Nov 13, 1997 Issued
Array ( [id] => 3891315 [patent_doc_number] => 05798939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'System for optimizing power network design reliability' [patent_app_type] => 1 [patent_app_number] => 8/950333 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7215 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798939.pdf [firstpage_image] =>[orig_patent_app_number] => 950333 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950333
System for optimizing power network design reliability Oct 13, 1997 Issued
Array ( [id] => 3782776 [patent_doc_number] => 05850539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Automated system for facilitating creation of a rack-mountable component personal computer' [patent_app_type] => 1 [patent_app_number] => 8/934534 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8586 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850539.pdf [firstpage_image] =>[orig_patent_app_number] => 934534 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934534
Automated system for facilitating creation of a rack-mountable component personal computer Sep 21, 1997 Issued
Array ( [id] => 4012047 [patent_doc_number] => 05993050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of and apparatus for extracting model parameters' [patent_app_type] => 1 [patent_app_number] => 8/933086 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10910 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/993/05993050.pdf [firstpage_image] =>[orig_patent_app_number] => 933086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933086
Method of and apparatus for extracting model parameters Sep 17, 1997 Issued
Array ( [id] => 3993550 [patent_doc_number] => 05949691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Logic circuit verification device to verify the logic circuit equivalence and a method therefor' [patent_app_type] => 1 [patent_app_number] => 8/911060 [patent_app_country] => US [patent_app_date] => 1997-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6969 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949691.pdf [firstpage_image] =>[orig_patent_app_number] => 911060 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911060
Logic circuit verification device to verify the logic circuit equivalence and a method therefor Aug 13, 1997 Issued
Array ( [id] => 4026710 [patent_doc_number] => 05880971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from semantic specifications and descriptions thereof' [patent_app_type] => 1 [patent_app_number] => 8/905917 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 10063 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880971.pdf [firstpage_image] =>[orig_patent_app_number] => 905917 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905917
Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from semantic specifications and descriptions thereof Aug 3, 1997 Issued
Array ( [id] => 3993549 [patent_doc_number] => 05910897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Specification and design of complex digital systems' [patent_app_type] => 1 [patent_app_number] => 8/890174 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 14954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910897.pdf [firstpage_image] =>[orig_patent_app_number] => 890174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890174
Specification and design of complex digital systems Jul 8, 1997 Issued
Array ( [id] => 3774547 [patent_doc_number] => 05844822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Simulation method for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/854544 [patent_app_country] => US [patent_app_date] => 1997-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6375 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844822.pdf [firstpage_image] =>[orig_patent_app_number] => 854544 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854544
Simulation method for semiconductor device May 11, 1997 Issued
Array ( [id] => 3838629 [patent_doc_number] => 05790975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Onboard navigational system' [patent_app_type] => 1 [patent_app_number] => 8/848384 [patent_app_country] => US [patent_app_date] => 1997-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5035 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790975.pdf [firstpage_image] =>[orig_patent_app_number] => 848384 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848384
Onboard navigational system May 7, 1997 Issued
Array ( [id] => 4004982 [patent_doc_number] => 05920492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Display list generator for fire simulation system' [patent_app_type] => 1 [patent_app_number] => 8/845666 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4465 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920492.pdf [firstpage_image] =>[orig_patent_app_number] => 845666 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/845666
Display list generator for fire simulation system Apr 24, 1997 Issued
Array ( [id] => 4077108 [patent_doc_number] => 05867399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description' [patent_app_type] => 1 [patent_app_number] => 8/847930 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 49 [patent_no_of_words] => 27512 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867399.pdf [firstpage_image] =>[orig_patent_app_number] => 847930 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847930
System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description Apr 20, 1997 Issued
Array ( [id] => 3986199 [patent_doc_number] => 05905658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Simulation method and apparatus of jaw movement' [patent_app_type] => 1 [patent_app_number] => 8/813082 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7250 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905658.pdf [firstpage_image] =>[orig_patent_app_number] => 813082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813082
Simulation method and apparatus of jaw movement Mar 6, 1997 Issued
Array ( [id] => 4025555 [patent_doc_number] => 05963459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => '3-D acoustic infinite element based on an ellipsoidal multipole expansion' [patent_app_type] => 1 [patent_app_number] => 8/812472 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8369 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963459.pdf [firstpage_image] =>[orig_patent_app_number] => 812472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812472
3-D acoustic infinite element based on an ellipsoidal multipole expansion Mar 5, 1997 Issued
Array ( [id] => 3970554 [patent_doc_number] => 05901063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'System and method for extracting parasitic impedance from an integrated circuit layout' [patent_app_type] => 1 [patent_app_number] => 8/804524 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7544 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901063.pdf [firstpage_image] =>[orig_patent_app_number] => 804524 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804524
System and method for extracting parasitic impedance from an integrated circuit layout Feb 20, 1997 Issued
Array ( [id] => 3891492 [patent_doc_number] => 05748474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Driving-force control system for a vehicle' [patent_app_type] => 1 [patent_app_number] => 8/794537 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 13089 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748474.pdf [firstpage_image] =>[orig_patent_app_number] => 794537 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794537
Driving-force control system for a vehicle Feb 2, 1997 Issued
Array ( [id] => 4036625 [patent_doc_number] => 05883808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Logic circuit optimization apparatus and its method' [patent_app_type] => 1 [patent_app_number] => 8/791755 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8134 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883808.pdf [firstpage_image] =>[orig_patent_app_number] => 791755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/791755
Logic circuit optimization apparatus and its method Jan 28, 1997 Issued
Array ( [id] => 3914910 [patent_doc_number] => 05898596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Adder which employs both carry look-ahead and carry select techniques' [patent_app_type] => 1 [patent_app_number] => 8/788619 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6593 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898596.pdf [firstpage_image] =>[orig_patent_app_number] => 788619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/788619
Adder which employs both carry look-ahead and carry select techniques Jan 23, 1997 Issued
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