Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3658867 [patent_doc_number] => 05606501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Method for damping crash-discrimination measures' [patent_app_type] => 1 [patent_app_number] => 8/288597 [patent_app_country] => US [patent_app_date] => 1994-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1961 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606501.pdf [firstpage_image] =>[orig_patent_app_number] => 288597 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/288597
Method for damping crash-discrimination measures Aug 9, 1994 Issued
Array ( [id] => 3427641 [patent_doc_number] => 05434795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Method of forming pattern having optical angle in charged particle exposure system' [patent_app_type] => 1 [patent_app_number] => 8/286254 [patent_app_country] => US [patent_app_date] => 1994-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 4178 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434795.pdf [firstpage_image] =>[orig_patent_app_number] => 286254 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/286254
Method of forming pattern having optical angle in charged particle exposure system Aug 7, 1994 Issued
08/287583 METHOD OF EXPRESSING A LOGIC CIRCUIT Aug 4, 1994 Abandoned
Array ( [id] => 3608020 [patent_doc_number] => 05559706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Apparatus for determining engine abnormality' [patent_app_type] => 1 [patent_app_number] => 8/276397 [patent_app_country] => US [patent_app_date] => 1994-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559706.pdf [firstpage_image] =>[orig_patent_app_number] => 276397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/276397
Apparatus for determining engine abnormality Jul 17, 1994 Issued
Array ( [id] => 3435390 [patent_doc_number] => 05416720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Method and apparatus for optimizing block shape in hierarchical IC design' [patent_app_type] => 1 [patent_app_number] => 8/272444 [patent_app_country] => US [patent_app_date] => 1994-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 7777 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416720.pdf [firstpage_image] =>[orig_patent_app_number] => 272444 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/272444
Method and apparatus for optimizing block shape in hierarchical IC design Jul 7, 1994 Issued
Array ( [id] => 3600922 [patent_doc_number] => 05568397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Logic circuit diagram editor system' [patent_app_type] => 1 [patent_app_number] => 8/271649 [patent_app_country] => US [patent_app_date] => 1994-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3965 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568397.pdf [firstpage_image] =>[orig_patent_app_number] => 271649 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/271649
Logic circuit diagram editor system Jul 6, 1994 Issued
Array ( [id] => 3432553 [patent_doc_number] => 05422823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Programmable gate array device having cascaded means for function definition' [patent_app_type] => 1 [patent_app_number] => 8/271872 [patent_app_country] => US [patent_app_date] => 1994-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 86 [patent_no_of_words] => 24984 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422823.pdf [firstpage_image] =>[orig_patent_app_number] => 271872 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/271872
Programmable gate array device having cascaded means for function definition Jul 6, 1994 Issued
Array ( [id] => 3113772 [patent_doc_number] => 05448496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system' [patent_app_type] => 1 [patent_app_number] => 8/270234 [patent_app_country] => US [patent_app_date] => 1994-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 82 [patent_no_of_words] => 46987 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448496.pdf [firstpage_image] =>[orig_patent_app_number] => 270234 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270234
Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system Jun 30, 1994 Issued
Array ( [id] => 3451068 [patent_doc_number] => 05430651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Position control system for a construction implement such as a road grader' [patent_app_type] => 1 [patent_app_number] => 8/269838 [patent_app_country] => US [patent_app_date] => 1994-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6083 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430651.pdf [firstpage_image] =>[orig_patent_app_number] => 269838 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/269838
Position control system for a construction implement such as a road grader Jun 30, 1994 Issued
Array ( [id] => 3529649 [patent_doc_number] => 05530654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'LSI logic synthesis device and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/269102 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4900 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530654.pdf [firstpage_image] =>[orig_patent_app_number] => 269102 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/269102
LSI logic synthesis device and method therefor Jun 29, 1994 Issued
Array ( [id] => 3600899 [patent_doc_number] => 05568395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Modeling and estimating crosstalk noise and detecting false logic' [patent_app_type] => 1 [patent_app_number] => 8/268920 [patent_app_country] => US [patent_app_date] => 1994-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 9196 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568395.pdf [firstpage_image] =>[orig_patent_app_number] => 268920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/268920
Modeling and estimating crosstalk noise and detecting false logic Jun 28, 1994 Issued
Array ( [id] => 3497110 [patent_doc_number] => 05475611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Circuit structure, semiconductor integrated circuit and path routing method and apparatus therefor' [patent_app_type] => 1 [patent_app_number] => 8/266310 [patent_app_country] => US [patent_app_date] => 1994-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7252 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475611.pdf [firstpage_image] =>[orig_patent_app_number] => 266310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/266310
Circuit structure, semiconductor integrated circuit and path routing method and apparatus therefor Jun 26, 1994 Issued
Array ( [id] => 3623746 [patent_doc_number] => 05510998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'System and method for generating component models' [patent_app_type] => 1 [patent_app_number] => 8/259027 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4280 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510998.pdf [firstpage_image] =>[orig_patent_app_number] => 259027 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/259027
System and method for generating component models Jun 12, 1994 Issued
Array ( [id] => 3501863 [patent_doc_number] => 05537330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Method for mapping in logic synthesis by logic classification' [patent_app_type] => 1 [patent_app_number] => 8/258314 [patent_app_country] => US [patent_app_date] => 1994-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5876 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537330.pdf [firstpage_image] =>[orig_patent_app_number] => 258314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/258314
Method for mapping in logic synthesis by logic classification Jun 9, 1994 Issued
Array ( [id] => 3597376 [patent_doc_number] => 05550749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'High level circuit design synthesis using transformations' [patent_app_type] => 1 [patent_app_number] => 8/254147 [patent_app_country] => US [patent_app_date] => 1994-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 7162 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550749.pdf [firstpage_image] =>[orig_patent_app_number] => 254147 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/254147
High level circuit design synthesis using transformations Jun 2, 1994 Issued
Array ( [id] => 3560231 [patent_doc_number] => 05572436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Method and system for creating and validating low level description of electronic design' [patent_app_type] => 1 [patent_app_number] => 8/252823 [patent_app_country] => US [patent_app_date] => 1994-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 28201 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572436.pdf [firstpage_image] =>[orig_patent_app_number] => 252823 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252823
Method and system for creating and validating low level description of electronic design Jun 1, 1994 Issued
Array ( [id] => 3562135 [patent_doc_number] => 05493508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Specification and design of complex digital systems' [patent_app_type] => 1 [patent_app_number] => 8/252231 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 14945 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493508.pdf [firstpage_image] =>[orig_patent_app_number] => 252231 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252231
Specification and design of complex digital systems May 31, 1994 Issued
Array ( [id] => 3560255 [patent_doc_number] => 05572437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models' [patent_app_type] => 1 [patent_app_number] => 8/246798 [patent_app_country] => US [patent_app_date] => 1994-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 16836 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572437.pdf [firstpage_image] =>[orig_patent_app_number] => 246798 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/246798
Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models May 19, 1994 Issued
Array ( [id] => 3603423 [patent_doc_number] => 05586275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Devices and systems with parallel logic unit operable on data memory locations, and methods' [patent_app_type] => 1 [patent_app_number] => 8/233477 [patent_app_country] => US [patent_app_date] => 1994-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 44 [patent_no_of_words] => 27984 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586275.pdf [firstpage_image] =>[orig_patent_app_number] => 233477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/233477
Devices and systems with parallel logic unit operable on data memory locations, and methods Apr 25, 1994 Issued
Array ( [id] => 3470516 [patent_doc_number] => 05392220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Method and system for organizing data' [patent_app_type] => 1 [patent_app_number] => 8/232856 [patent_app_country] => US [patent_app_date] => 1994-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6753 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392220.pdf [firstpage_image] =>[orig_patent_app_number] => 232856 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/232856
Method and system for organizing data Apr 24, 1994 Issued
Menu