
Vincent N. Trans
Examiner (ID: 10207)
| Most Active Art Unit | 2304 |
| Art Unit(s) | 2763, 2304, 2899, OPET, 2787 |
| Total Applications | 1054 |
| Issued Applications | 820 |
| Pending Applications | 21 |
| Abandoned Applications | 213 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3658867
[patent_doc_number] => 05606501
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Method for damping crash-discrimination measures'
[patent_app_type] => 1
[patent_app_number] => 8/288597
[patent_app_country] => US
[patent_app_date] => 1994-08-10
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[patent_no_of_words] => 1961
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[pdf_file] => patents/05/606/05606501.pdf
[firstpage_image] =>[orig_patent_app_number] => 288597
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/288597 | Method for damping crash-discrimination measures | Aug 9, 1994 | Issued |
Array
(
[id] => 3427641
[patent_doc_number] => 05434795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-18
[patent_title] => 'Method of forming pattern having optical angle in charged particle exposure system'
[patent_app_type] => 1
[patent_app_number] => 8/286254
[patent_app_country] => US
[patent_app_date] => 1994-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[firstpage_image] =>[orig_patent_app_number] => 286254
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/286254 | Method of forming pattern having optical angle in charged particle exposure system | Aug 7, 1994 | Issued |
| 08/287583 | METHOD OF EXPRESSING A LOGIC CIRCUIT | Aug 4, 1994 | Abandoned |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Apparatus for determining engine abnormality'
[patent_app_type] => 1
[patent_app_number] => 8/276397
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[patent_app_date] => 1994-07-18
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Array
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[patent_kind] => NA
[patent_issue_date] => 1995-05-16
[patent_title] => 'Method and apparatus for optimizing block shape in hierarchical IC design'
[patent_app_type] => 1
[patent_app_number] => 8/272444
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[patent_app_date] => 1994-07-08
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[firstpage_image] =>[orig_patent_app_number] => 272444
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/272444 | Method and apparatus for optimizing block shape in hierarchical IC design | Jul 7, 1994 | Issued |
Array
(
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[patent_doc_number] => 05568397
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[patent_issue_date] => 1996-10-22
[patent_title] => 'Logic circuit diagram editor system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/271649 | Logic circuit diagram editor system | Jul 6, 1994 | Issued |
Array
(
[id] => 3432553
[patent_doc_number] => 05422823
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[patent_issue_date] => 1995-06-06
[patent_title] => 'Programmable gate array device having cascaded means for function definition'
[patent_app_type] => 1
[patent_app_number] => 8/271872
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/271872 | Programmable gate array device having cascaded means for function definition | Jul 6, 1994 | Issued |
Array
(
[id] => 3113772
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[patent_title] => 'Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system'
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[firstpage_image] =>[orig_patent_app_number] => 270234
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/270234 | Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system | Jun 30, 1994 | Issued |
Array
(
[id] => 3451068
[patent_doc_number] => 05430651
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Position control system for a construction implement such as a road grader'
[patent_app_type] => 1
[patent_app_number] => 8/269838
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[patent_app_date] => 1994-07-01
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[firstpage_image] =>[orig_patent_app_number] => 269838
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269838 | Position control system for a construction implement such as a road grader | Jun 30, 1994 | Issued |
Array
(
[id] => 3529649
[patent_doc_number] => 05530654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'LSI logic synthesis device and method therefor'
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[patent_app_number] => 8/269102
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269102 | LSI logic synthesis device and method therefor | Jun 29, 1994 | Issued |
Array
(
[id] => 3600899
[patent_doc_number] => 05568395
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[patent_issue_date] => 1996-10-22
[patent_title] => 'Modeling and estimating crosstalk noise and detecting false logic'
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[patent_app_date] => 1994-06-29
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[pdf_file] => patents/05/568/05568395.pdf
[firstpage_image] =>[orig_patent_app_number] => 268920
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/268920 | Modeling and estimating crosstalk noise and detecting false logic | Jun 28, 1994 | Issued |
Array
(
[id] => 3497110
[patent_doc_number] => 05475611
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[patent_issue_date] => 1995-12-12
[patent_title] => 'Circuit structure, semiconductor integrated circuit and path routing method and apparatus therefor'
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[firstpage_image] =>[orig_patent_app_number] => 266310
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/266310 | Circuit structure, semiconductor integrated circuit and path routing method and apparatus therefor | Jun 26, 1994 | Issued |
Array
(
[id] => 3623746
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[patent_title] => 'System and method for generating component models'
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Array
(
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Array
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Array
(
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Array
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Array
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