Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3497035 [patent_doc_number] => 05475607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Method of target generation for multilevel hierarchical circuit designs' [patent_app_type] => 1 [patent_app_number] => 8/226603 [patent_app_country] => US [patent_app_date] => 1994-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9645 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475607.pdf [firstpage_image] =>[orig_patent_app_number] => 226603 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/226603
Method of target generation for multilevel hierarchical circuit designs Apr 11, 1994 Issued
Array ( [id] => 3432456 [patent_doc_number] => 05459673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Method and apparatus for optimizing electronic circuits' [patent_app_type] => 1 [patent_app_number] => 8/225492 [patent_app_country] => US [patent_app_date] => 1994-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7052 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459673.pdf [firstpage_image] =>[orig_patent_app_number] => 225492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/225492
Method and apparatus for optimizing electronic circuits Apr 10, 1994 Issued
Array ( [id] => 3566443 [patent_doc_number] => 05502644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Process and apparatus for auditing crosstalk and characteristic impedances of printed wiring boards' [patent_app_type] => 1 [patent_app_number] => 8/225012 [patent_app_country] => US [patent_app_date] => 1994-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3949 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502644.pdf [firstpage_image] =>[orig_patent_app_number] => 225012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/225012
Process and apparatus for auditing crosstalk and characteristic impedances of printed wiring boards Apr 6, 1994 Issued
Array ( [id] => 3559044 [patent_doc_number] => 05548524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Expression promotion for hierarchical netlisting' [patent_app_type] => 1 [patent_app_number] => 8/223924 [patent_app_country] => US [patent_app_date] => 1994-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3057 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548524.pdf [firstpage_image] =>[orig_patent_app_number] => 223924 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/223924
Expression promotion for hierarchical netlisting Apr 5, 1994 Issued
Array ( [id] => 3535815 [patent_doc_number] => 05528511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Delay time verifier and delay time verification method for logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/223722 [patent_app_country] => US [patent_app_date] => 1994-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3957 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528511.pdf [firstpage_image] =>[orig_patent_app_number] => 223722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/223722
Delay time verifier and delay time verification method for logic circuits Apr 5, 1994 Issued
Array ( [id] => 3135289 [patent_doc_number] => 05436850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Method to identify protein sequences that fold into a known three-dimensional structure' [patent_app_type] => 1 [patent_app_number] => 8/218685 [patent_app_country] => US [patent_app_date] => 1994-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8868 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436850.pdf [firstpage_image] =>[orig_patent_app_number] => 218685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/218685
Method to identify protein sequences that fold into a known three-dimensional structure Mar 27, 1994 Issued
Array ( [id] => 3563144 [patent_doc_number] => 05519630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'LSI automated design system' [patent_app_type] => 1 [patent_app_number] => 8/210468 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 56 [patent_no_of_words] => 17654 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519630.pdf [firstpage_image] =>[orig_patent_app_number] => 210468 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/210468
LSI automated design system Mar 20, 1994 Issued
Array ( [id] => 3537000 [patent_doc_number] => 05541861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Logic simulator' [patent_app_type] => 1 [patent_app_number] => 8/212788 [patent_app_country] => US [patent_app_date] => 1994-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 8155 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541861.pdf [firstpage_image] =>[orig_patent_app_number] => 212788 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/212788
Logic simulator Mar 14, 1994 Issued
Array ( [id] => 3565426 [patent_doc_number] => 05544068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'System and method for optimizing delays in semiconductor circuits' [patent_app_type] => 1 [patent_app_number] => 8/209331 [patent_app_country] => US [patent_app_date] => 1994-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6275 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544068.pdf [firstpage_image] =>[orig_patent_app_number] => 209331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/209331
System and method for optimizing delays in semiconductor circuits Mar 8, 1994 Issued
08/209127 EMULATION DEVICES, SYSTEMS AND METHODS WITH DISTRIBUTED CONTROL OF TEST INTERFACES IN CLOCK DOMAINS Mar 8, 1994 Abandoned
Array ( [id] => 3540775 [patent_doc_number] => 05583787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Method and data processing system for determining electrical circuit path delays' [patent_app_type] => 1 [patent_app_number] => 8/207505 [patent_app_country] => US [patent_app_date] => 1994-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8445 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583787.pdf [firstpage_image] =>[orig_patent_app_number] => 207505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/207505
Method and data processing system for determining electrical circuit path delays Mar 7, 1994 Issued
Array ( [id] => 3530025 [patent_doc_number] => 05490084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method and apparatus for detecting bent leads in electronic components' [patent_app_type] => 1 [patent_app_number] => 8/209201 [patent_app_country] => US [patent_app_date] => 1994-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 4747 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490084.pdf [firstpage_image] =>[orig_patent_app_number] => 209201 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/209201
Method and apparatus for detecting bent leads in electronic components Mar 3, 1994 Issued
Array ( [id] => 3560218 [patent_doc_number] => 05572435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Method for designing a transformer' [patent_app_type] => 1 [patent_app_number] => 8/202610 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1930 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572435.pdf [firstpage_image] =>[orig_patent_app_number] => 202610 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/202610
Method for designing a transformer Feb 27, 1994 Issued
Array ( [id] => 3122466 [patent_doc_number] => 05414640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Method and apparatus for adaptive demand limiting electric consumption through load shedding' [patent_app_type] => 1 [patent_app_number] => 8/216601 [patent_app_country] => US [patent_app_date] => 1994-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9306 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414640.pdf [firstpage_image] =>[orig_patent_app_number] => 216601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216601
Method and apparatus for adaptive demand limiting electric consumption through load shedding Feb 22, 1994 Issued
Array ( [id] => 3122466 [patent_doc_number] => 05414640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Method and apparatus for adaptive demand limiting electric consumption through load shedding' [patent_app_type] => 1 [patent_app_number] => 8/216601 [patent_app_country] => US [patent_app_date] => 1994-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9306 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414640.pdf [firstpage_image] =>[orig_patent_app_number] => 216601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216601
Method and apparatus for adaptive demand limiting electric consumption through load shedding Feb 22, 1994 Issued
Array ( [id] => 3421667 [patent_doc_number] => 05444628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Computer controlled flow of nitrous oxide injected into an internal combustion engine' [patent_app_type] => 1 [patent_app_number] => 8/195252 [patent_app_country] => US [patent_app_date] => 1994-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9287 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444628.pdf [firstpage_image] =>[orig_patent_app_number] => 195252 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/195252
Computer controlled flow of nitrous oxide injected into an internal combustion engine Feb 13, 1994 Issued
Array ( [id] => 3553507 [patent_doc_number] => 05555201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information' [patent_app_type] => 1 [patent_app_number] => 8/196337 [patent_app_country] => US [patent_app_date] => 1994-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 65 [patent_no_of_words] => 47302 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555201.pdf [firstpage_image] =>[orig_patent_app_number] => 196337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/196337
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information Feb 9, 1994 Issued
Array ( [id] => 3673534 [patent_doc_number] => 05598344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Method and system for creating, validating, and scaling structural description of electronic device' [patent_app_type] => 1 [patent_app_number] => 8/193306 [patent_app_country] => US [patent_app_date] => 1994-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 29585 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598344.pdf [firstpage_image] =>[orig_patent_app_number] => 193306 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/193306
Method and system for creating, validating, and scaling structural description of electronic device Feb 7, 1994 Issued
08/194622 METHOD OF ARRANGING COMPONENTS IN SEMICONDUCTOR DEVICE Feb 6, 1994 Abandoned
Array ( [id] => 3435088 [patent_doc_number] => 05404300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Automobile integrated wiring system' [patent_app_type] => 1 [patent_app_number] => 8/191725 [patent_app_country] => US [patent_app_date] => 1994-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2577 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404300.pdf [firstpage_image] =>[orig_patent_app_number] => 191725 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/191725
Automobile integrated wiring system Feb 3, 1994 Issued
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