Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3492302 [patent_doc_number] => 05446675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Developing method and apparatus of hierarchical graphic data for use in a semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/189033 [patent_app_country] => US [patent_app_date] => 1994-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4040 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446675.pdf [firstpage_image] =>[orig_patent_app_number] => 189033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/189033
Developing method and apparatus of hierarchical graphic data for use in a semiconductor integrated circuit Jan 30, 1994 Issued
Array ( [id] => 3013776 [patent_doc_number] => 05375069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Wiring routes in a plurality of wiring layers' [patent_app_type] => 1 [patent_app_number] => 8/184753 [patent_app_country] => US [patent_app_date] => 1994-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 38 [patent_no_of_words] => 9304 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375069.pdf [firstpage_image] =>[orig_patent_app_number] => 184753 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/184753
Wiring routes in a plurality of wiring layers Jan 20, 1994 Issued
Array ( [id] => 3113735 [patent_doc_number] => 05448494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Mask data processing apparatus for integrated circuit production' [patent_app_type] => 1 [patent_app_number] => 8/180498 [patent_app_country] => US [patent_app_date] => 1994-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 2952 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448494.pdf [firstpage_image] =>[orig_patent_app_number] => 180498 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/180498
Mask data processing apparatus for integrated circuit production Jan 11, 1994 Issued
Array ( [id] => 3664253 [patent_doc_number] => 05623428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method for developing computer animation' [patent_app_type] => 1 [patent_app_number] => 8/178217 [patent_app_country] => US [patent_app_date] => 1994-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6678 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623428.pdf [firstpage_image] =>[orig_patent_app_number] => 178217 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/178217
Method for developing computer animation Jan 5, 1994 Issued
08/175658 METHOD AND APPARATUS FOR CONVERTING FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS INTO MASK-PROGRAMMABLE LOGIC CELL IMPLEMENTATIONS Dec 29, 1993 Abandoned
08/175981 RECONFIGURABLE HARDWARE EMULATION SYSTEM Dec 29, 1993 Abandoned
Array ( [id] => 3489329 [patent_doc_number] => 05400262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Universal interconnect matrix array' [patent_app_type] => 1 [patent_app_number] => 8/173729 [patent_app_country] => US [patent_app_date] => 1993-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5259 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/400/05400262.pdf [firstpage_image] =>[orig_patent_app_number] => 173729 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/173729
Universal interconnect matrix array Dec 26, 1993 Issued
08/173414 FIELD PROGRAMMABLE MIXED (ANALOG/DIGIAL) ARRAY DEVICE Dec 22, 1993 Abandoned
Array ( [id] => 3130398 [patent_doc_number] => 05384710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Circuit level netlist generation' [patent_app_type] => 1 [patent_app_number] => 8/173808 [patent_app_country] => US [patent_app_date] => 1993-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 81 [patent_no_of_words] => 8066 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384710.pdf [firstpage_image] =>[orig_patent_app_number] => 173808 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/173808
Circuit level netlist generation Dec 21, 1993 Issued
Array ( [id] => 3515139 [patent_doc_number] => 05515293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Method and apparatus for generating a linked data structure for integrated circuit layout' [patent_app_type] => 1 [patent_app_number] => 8/172449 [patent_app_country] => US [patent_app_date] => 1993-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 6434 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515293.pdf [firstpage_image] =>[orig_patent_app_number] => 172449 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/172449
Method and apparatus for generating a linked data structure for integrated circuit layout Dec 21, 1993 Issued
Array ( [id] => 3565440 [patent_doc_number] => 05544069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Structure having different levels of programmable integrated circuits interconnected through bus lines for interconnecting electronic components' [patent_app_type] => 1 [patent_app_number] => 8/171992 [patent_app_country] => US [patent_app_date] => 1993-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 8943 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544069.pdf [firstpage_image] =>[orig_patent_app_number] => 171992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/171992
Structure having different levels of programmable integrated circuits interconnected through bus lines for interconnecting electronic components Dec 21, 1993 Issued
Array ( [id] => 3889724 [patent_doc_number] => 05729469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Wiring method and system for integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/162353 [patent_app_country] => US [patent_app_date] => 1993-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4664 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729469.pdf [firstpage_image] =>[orig_patent_app_number] => 162353 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/162353
Wiring method and system for integrated circuit Dec 6, 1993 Issued
Array ( [id] => 3566472 [patent_doc_number] => 05502646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Selection of partial scan flip-flops to break feedback cycles' [patent_app_type] => 1 [patent_app_number] => 8/161140 [patent_app_country] => US [patent_app_date] => 1993-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6061 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502646.pdf [firstpage_image] =>[orig_patent_app_number] => 161140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/161140
Selection of partial scan flip-flops to break feedback cycles Dec 1, 1993 Issued
Array ( [id] => 3566488 [patent_doc_number] => 05502647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Resynthesis and retiming for optimum partial scan testing' [patent_app_type] => 1 [patent_app_number] => 8/161221 [patent_app_country] => US [patent_app_date] => 1993-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 8341 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502647.pdf [firstpage_image] =>[orig_patent_app_number] => 161221 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/161221
Resynthesis and retiming for optimum partial scan testing Nov 30, 1993 Issued
Array ( [id] => 3602348 [patent_doc_number] => 05521834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/159976 [patent_app_country] => US [patent_app_date] => 1993-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3641 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521834.pdf [firstpage_image] =>[orig_patent_app_number] => 159976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/159976
Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits Nov 29, 1993 Issued
Array ( [id] => 3116571 [patent_doc_number] => 05418723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Method of determining a set value of the assisting force in a power steering system' [patent_app_type] => 1 [patent_app_number] => 8/158359 [patent_app_country] => US [patent_app_date] => 1993-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3684 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418723.pdf [firstpage_image] =>[orig_patent_app_number] => 158359 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/158359
Method of determining a set value of the assisting force in a power steering system Nov 28, 1993 Issued
Array ( [id] => 3430151 [patent_doc_number] => 05390118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Automatic lateral guidance control system' [patent_app_type] => 1 [patent_app_number] => 8/156944 [patent_app_country] => US [patent_app_date] => 1993-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 7934 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390118.pdf [firstpage_image] =>[orig_patent_app_number] => 156944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/156944
Automatic lateral guidance control system Nov 23, 1993 Issued
Array ( [id] => 3065620 [patent_doc_number] => 05357432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-18 [patent_title] => 'Automatic lateral guidance control system' [patent_app_type] => 1 [patent_app_number] => 8/156943 [patent_app_country] => US [patent_app_date] => 1993-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6260 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/357/05357432.pdf [firstpage_image] =>[orig_patent_app_number] => 156943 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/156943
Automatic lateral guidance control system Nov 23, 1993 Issued
Array ( [id] => 3085565 [patent_doc_number] => 05323323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Franking machine system' [patent_app_type] => 1 [patent_app_number] => 8/155245 [patent_app_country] => US [patent_app_date] => 1993-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3427 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/323/05323323.pdf [firstpage_image] =>[orig_patent_app_number] => 155245 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/155245
Franking machine system Nov 21, 1993 Issued
08/151587 METHOD AND SYSTEM FOR ORGANIZING AND ACCESSING DATA Nov 11, 1993 Abandoned
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