| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[id] => 3501892
[patent_doc_number] => 05537332
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Stack macro order optimizing method'
[patent_app_type] => 1
[patent_app_number] => 8/146820
[patent_app_country] => US
[patent_app_date] => 1993-11-02
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[firstpage_image] =>[orig_patent_app_number] => 146820
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/146820 | Stack macro order optimizing method | Nov 1, 1993 | Issued |
Array
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[id] => 3049061
[patent_doc_number] => 05377122
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-27
[patent_title] => 'Logic compiler for design of circuit models'
[patent_app_type] => 1
[patent_app_number] => 8/147419
[patent_app_country] => US
[patent_app_date] => 1993-11-01
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[pdf_file] => patents/05/377/05377122.pdf
[firstpage_image] =>[orig_patent_app_number] => 147419
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/147419 | Logic compiler for design of circuit models | Oct 31, 1993 | Issued |
Array
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[id] => 3466398
[patent_doc_number] => 05402358
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-28
[patent_title] => 'Method and structure for the automated design of analog integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/147465
[patent_app_country] => US
[patent_app_date] => 1993-10-29
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 147465
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/147465 | Method and structure for the automated design of analog integrated circuits | Oct 28, 1993 | Issued |
Array
(
[id] => 3562121
[patent_doc_number] => 05493507
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/136203
[patent_app_country] => US
[patent_app_date] => 1993-10-15
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[pdf_file] => patents/05/493/05493507.pdf
[firstpage_image] =>[orig_patent_app_number] => 136203
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/136203 | Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and method thereof | Oct 14, 1993 | Issued |
Array
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[id] => 3697116
[patent_doc_number] => 05644497
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array'
[patent_app_type] => 1
[patent_app_number] => 8/132992
[patent_app_country] => US
[patent_app_date] => 1993-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/644/05644497.pdf
[firstpage_image] =>[orig_patent_app_number] => 132992
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/132992 | Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array | Oct 5, 1993 | Issued |
| 08/132520 | MULTIPLE SOURCE EQUALIZATION DESIGN FOR GATE ARRAYS AND EMBEDDED ARRAYS | Oct 5, 1993 | Abandoned |
Array
(
[id] => 3673520
[patent_doc_number] => 05598343
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[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Method of segmenting an FPGA channel architecture for maximum routability and performance'
[patent_app_type] => 1
[patent_app_number] => 8/130605
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/130605 | Method of segmenting an FPGA channel architecture for maximum routability and performance | Sep 30, 1993 | Issued |
Array
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[id] => 3024898
[patent_doc_number] => 05341299
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-23
[patent_title] => 'Gas motor control'
[patent_app_type] => 1
[patent_app_number] => 8/128316
[patent_app_country] => US
[patent_app_date] => 1993-09-28
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[pdf_file] => patents/05/341/05341299.pdf
[firstpage_image] =>[orig_patent_app_number] => 128316
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/128316 | Gas motor control | Sep 27, 1993 | Issued |
Array
(
[id] => 3122466
[patent_doc_number] => 05414640
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Method and apparatus for adaptive demand limiting electric consumption through load shedding'
[patent_app_type] => 1
[patent_app_number] => 8/216601
[patent_app_country] => US
[patent_app_date] => 1994-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/414/05414640.pdf
[firstpage_image] =>[orig_patent_app_number] => 216601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/216601 | Hydro-pneumatic flush system for toilets | Sep 26, 1993 | Issued |
Array
(
[id] => 3122466
[patent_doc_number] => 05414640
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Method and apparatus for adaptive demand limiting electric consumption through load shedding'
[patent_app_type] => 1
[patent_app_number] => 8/216601
[patent_app_country] => US
[patent_app_date] => 1994-02-23
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[firstpage_image] =>[orig_patent_app_number] => 216601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/216601 | Hydro-pneumatic flush system for toilets | Sep 26, 1993 | Issued |
| 08/123036 | METHOD OF FORMING PATTERN HAVING OPTIONAL ANGLE IN CHARGED PARTICLE EXPOSURE SYSTEM | Sep 19, 1993 | Abandoned |
| 08/122132 | METHOD AND APPARATUS FOR OPTIMIZING ELECTRONIC CIRCUITS | Sep 13, 1993 | Abandoned |
Array
(
[id] => 3428212
[patent_doc_number] => 05479355
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'System and method for a closed loop operation of schematic designs with electrical hardware'
[patent_app_type] => 1
[patent_app_number] => 8/121926
[patent_app_country] => US
[patent_app_date] => 1993-09-14
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[pdf_file] => patents/05/479/05479355.pdf
[firstpage_image] =>[orig_patent_app_number] => 121926
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/121926 | System and method for a closed loop operation of schematic designs with electrical hardware | Sep 13, 1993 | Issued |
Array
(
[id] => 3498656
[patent_doc_number] => 05471409
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Logic simulation apparatus and circuit simulation apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/120438
[patent_app_country] => US
[patent_app_date] => 1993-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[pdf_file] => patents/05/471/05471409.pdf
[firstpage_image] =>[orig_patent_app_number] => 120438
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/120438 | Logic simulation apparatus and circuit simulation apparatus | Sep 13, 1993 | Issued |
Array
(
[id] => 3562151
[patent_doc_number] => 05493509
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Method of and apparatus for generating mask layouts'
[patent_app_type] => 1
[patent_app_number] => 8/115144
[patent_app_country] => US
[patent_app_date] => 1993-09-02
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[firstpage_image] =>[orig_patent_app_number] => 115144
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/115144 | Method of and apparatus for generating mask layouts | Sep 1, 1993 | Issued |
Array
(
[id] => 3558938
[patent_doc_number] => 05548517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Aircraft weight and center of gravity indicator'
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[patent_app_country] => US
[patent_app_date] => 1993-08-27
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[firstpage_image] =>[orig_patent_app_number] => 113286
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/113286 | Aircraft weight and center of gravity indicator | Aug 26, 1993 | Issued |
Array
(
[id] => 3534376
[patent_doc_number] => 05504690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Automatic logic designing method and system'
[patent_app_type] => 1
[patent_app_number] => 8/108044
[patent_app_country] => US
[patent_app_date] => 1993-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => patents/05/504/05504690.pdf
[firstpage_image] =>[orig_patent_app_number] => 108044
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/108044 | Automatic logic designing method and system | Aug 15, 1993 | Issued |
| 08/103946 | HIERARCHICAL FLOORPLANNER FOR GATE ARRAY DESIGN LAYOUT | Aug 9, 1993 | Abandoned |
| 08/102616 | METHOD FOR DESIGNING A LARGE SCALE INTEGRATED (LSI) LAYOUT | Aug 4, 1993 | Abandoned |
Array
(
[id] => 3467068
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/100117 | Apparatus for computing power consumption of MOS transistor logic function block | Jul 29, 1993 | Issued |