Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3501892 [patent_doc_number] => 05537332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Stack macro order optimizing method' [patent_app_type] => 1 [patent_app_number] => 8/146820 [patent_app_country] => US [patent_app_date] => 1993-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4168 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537332.pdf [firstpage_image] =>[orig_patent_app_number] => 146820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/146820
Stack macro order optimizing method Nov 1, 1993 Issued
Array ( [id] => 3049061 [patent_doc_number] => 05377122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Logic compiler for design of circuit models' [patent_app_type] => 1 [patent_app_number] => 8/147419 [patent_app_country] => US [patent_app_date] => 1993-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4250 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377122.pdf [firstpage_image] =>[orig_patent_app_number] => 147419 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/147419
Logic compiler for design of circuit models Oct 31, 1993 Issued
Array ( [id] => 3466398 [patent_doc_number] => 05402358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Method and structure for the automated design of analog integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/147465 [patent_app_country] => US [patent_app_date] => 1993-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4587 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402358.pdf [firstpage_image] =>[orig_patent_app_number] => 147465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/147465
Method and structure for the automated design of analog integrated circuits Oct 28, 1993 Issued
Array ( [id] => 3562121 [patent_doc_number] => 05493507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/136203 [patent_app_country] => US [patent_app_date] => 1993-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6028 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493507.pdf [firstpage_image] =>[orig_patent_app_number] => 136203 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/136203
Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and method thereof Oct 14, 1993 Issued
Array ( [id] => 3697116 [patent_doc_number] => 05644497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array' [patent_app_type] => 1 [patent_app_number] => 8/132992 [patent_app_country] => US [patent_app_date] => 1993-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6724 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644497.pdf [firstpage_image] =>[orig_patent_app_number] => 132992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/132992
Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential logic array Oct 5, 1993 Issued
08/132520 MULTIPLE SOURCE EQUALIZATION DESIGN FOR GATE ARRAYS AND EMBEDDED ARRAYS Oct 5, 1993 Abandoned
Array ( [id] => 3673520 [patent_doc_number] => 05598343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Method of segmenting an FPGA channel architecture for maximum routability and performance' [patent_app_type] => 1 [patent_app_number] => 8/130605 [patent_app_country] => US [patent_app_date] => 1993-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6162 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598343.pdf [firstpage_image] =>[orig_patent_app_number] => 130605 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/130605
Method of segmenting an FPGA channel architecture for maximum routability and performance Sep 30, 1993 Issued
Array ( [id] => 3024898 [patent_doc_number] => 05341299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Gas motor control' [patent_app_type] => 1 [patent_app_number] => 8/128316 [patent_app_country] => US [patent_app_date] => 1993-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 930 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341299.pdf [firstpage_image] =>[orig_patent_app_number] => 128316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/128316
Gas motor control Sep 27, 1993 Issued
Array ( [id] => 3122466 [patent_doc_number] => 05414640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Method and apparatus for adaptive demand limiting electric consumption through load shedding' [patent_app_type] => 1 [patent_app_number] => 8/216601 [patent_app_country] => US [patent_app_date] => 1994-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9306 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414640.pdf [firstpage_image] =>[orig_patent_app_number] => 216601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216601
Hydro-pneumatic flush system for toilets Sep 26, 1993 Issued
Array ( [id] => 3122466 [patent_doc_number] => 05414640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Method and apparatus for adaptive demand limiting electric consumption through load shedding' [patent_app_type] => 1 [patent_app_number] => 8/216601 [patent_app_country] => US [patent_app_date] => 1994-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9306 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414640.pdf [firstpage_image] =>[orig_patent_app_number] => 216601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216601
Hydro-pneumatic flush system for toilets Sep 26, 1993 Issued
08/123036 METHOD OF FORMING PATTERN HAVING OPTIONAL ANGLE IN CHARGED PARTICLE EXPOSURE SYSTEM Sep 19, 1993 Abandoned
08/122132 METHOD AND APPARATUS FOR OPTIMIZING ELECTRONIC CIRCUITS Sep 13, 1993 Abandoned
Array ( [id] => 3428212 [patent_doc_number] => 05479355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'System and method for a closed loop operation of schematic designs with electrical hardware' [patent_app_type] => 1 [patent_app_number] => 8/121926 [patent_app_country] => US [patent_app_date] => 1993-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5732 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479355.pdf [firstpage_image] =>[orig_patent_app_number] => 121926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/121926
System and method for a closed loop operation of schematic designs with electrical hardware Sep 13, 1993 Issued
Array ( [id] => 3498656 [patent_doc_number] => 05471409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Logic simulation apparatus and circuit simulation apparatus' [patent_app_type] => 1 [patent_app_number] => 8/120438 [patent_app_country] => US [patent_app_date] => 1993-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11419 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471409.pdf [firstpage_image] =>[orig_patent_app_number] => 120438 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/120438
Logic simulation apparatus and circuit simulation apparatus Sep 13, 1993 Issued
Array ( [id] => 3562151 [patent_doc_number] => 05493509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Method of and apparatus for generating mask layouts' [patent_app_type] => 1 [patent_app_number] => 8/115144 [patent_app_country] => US [patent_app_date] => 1993-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 4046 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493509.pdf [firstpage_image] =>[orig_patent_app_number] => 115144 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/115144
Method of and apparatus for generating mask layouts Sep 1, 1993 Issued
Array ( [id] => 3558938 [patent_doc_number] => 05548517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Aircraft weight and center of gravity indicator' [patent_app_type] => 1 [patent_app_number] => 8/113286 [patent_app_country] => US [patent_app_date] => 1993-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5643 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548517.pdf [firstpage_image] =>[orig_patent_app_number] => 113286 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/113286
Aircraft weight and center of gravity indicator Aug 26, 1993 Issued
Array ( [id] => 3534376 [patent_doc_number] => 05504690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Automatic logic designing method and system' [patent_app_type] => 1 [patent_app_number] => 8/108044 [patent_app_country] => US [patent_app_date] => 1993-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 8191 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504690.pdf [firstpage_image] =>[orig_patent_app_number] => 108044 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/108044
Automatic logic designing method and system Aug 15, 1993 Issued
08/103946 HIERARCHICAL FLOORPLANNER FOR GATE ARRAY DESIGN LAYOUT Aug 9, 1993 Abandoned
08/102616 METHOD FOR DESIGNING A LARGE SCALE INTEGRATED (LSI) LAYOUT Aug 4, 1993 Abandoned
Array ( [id] => 3467068 [patent_doc_number] => 05473548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Apparatus for computing power consumption of MOS transistor logic function block' [patent_app_type] => 1 [patent_app_number] => 8/100117 [patent_app_country] => US [patent_app_date] => 1993-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3947 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473548.pdf [firstpage_image] =>[orig_patent_app_number] => 100117 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/100117
Apparatus for computing power consumption of MOS transistor logic function block Jul 29, 1993 Issued
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