Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3727105 [patent_doc_number] => 05617327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Method for entering state flow diagrams using schematic editor programs' [patent_app_type] => 1 [patent_app_number] => 8/100521 [patent_app_country] => US [patent_app_date] => 1993-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 65 [patent_no_of_words] => 21577 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617327.pdf [firstpage_image] =>[orig_patent_app_number] => 100521 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/100521
Method for entering state flow diagrams using schematic editor programs Jul 29, 1993 Issued
Array ( [id] => 3483110 [patent_doc_number] => 05428540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Anti-lock control method and apparatus for automotive vehicle' [patent_app_type] => 1 [patent_app_number] => 8/099406 [patent_app_country] => US [patent_app_date] => 1993-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5576 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428540.pdf [firstpage_image] =>[orig_patent_app_number] => 099406 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/099406
Anti-lock control method and apparatus for automotive vehicle Jul 29, 1993 Issued
Array ( [id] => 3857832 [patent_doc_number] => 05719774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'System and method for relating disparate data models of physical objects' [patent_app_type] => 1 [patent_app_number] => 8/099303 [patent_app_country] => US [patent_app_date] => 1993-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3824 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719774.pdf [firstpage_image] =>[orig_patent_app_number] => 099303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/099303
System and method for relating disparate data models of physical objects Jul 28, 1993 Issued
Array ( [id] => 3582165 [patent_doc_number] => 05539671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Food temperature control system' [patent_app_type] => 1 [patent_app_number] => 8/098014 [patent_app_country] => US [patent_app_date] => 1993-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2017 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539671.pdf [firstpage_image] =>[orig_patent_app_number] => 098014 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/098014
Food temperature control system Jul 25, 1993 Issued
Array ( [id] => 3572276 [patent_doc_number] => 05526274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Digital potentiometer with stackable configuration system' [patent_app_type] => 1 [patent_app_number] => 8/089923 [patent_app_country] => US [patent_app_date] => 1993-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7554 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526274.pdf [firstpage_image] =>[orig_patent_app_number] => 089923 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/089923
Digital potentiometer with stackable configuration system Jul 8, 1993 Issued
Array ( [id] => 3437815 [patent_doc_number] => 05463561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'High capacity netlist comparison' [patent_app_type] => 1 [patent_app_number] => 8/085639 [patent_app_country] => US [patent_app_date] => 1993-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7471 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463561.pdf [firstpage_image] =>[orig_patent_app_number] => 085639 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/085639
High capacity netlist comparison Jun 29, 1993 Issued
Array ( [id] => 3437845 [patent_doc_number] => 05463563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Automatic logic model generation from schematic data base' [patent_app_type] => 1 [patent_app_number] => 8/085658 [patent_app_country] => US [patent_app_date] => 1993-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5927 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463563.pdf [firstpage_image] =>[orig_patent_app_number] => 085658 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/085658
Automatic logic model generation from schematic data base Jun 29, 1993 Issued
Array ( [id] => 3130343 [patent_doc_number] => 05384707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Diagnostic airflow measurement' [patent_app_type] => 1 [patent_app_number] => 8/083205 [patent_app_country] => US [patent_app_date] => 1993-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1873 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384707.pdf [firstpage_image] =>[orig_patent_app_number] => 083205 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/083205
Diagnostic airflow measurement Jun 28, 1993 Issued
Array ( [id] => 3491040 [patent_doc_number] => 05406488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Correction of errors in autopilots' [patent_app_type] => 1 [patent_app_number] => 8/083332 [patent_app_country] => US [patent_app_date] => 1993-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5438 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406488.pdf [firstpage_image] =>[orig_patent_app_number] => 083332 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/083332
Correction of errors in autopilots Jun 28, 1993 Issued
Array ( [id] => 3111143 [patent_doc_number] => 05315535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Automatic router capable of searching for a new wiring with reference to connection failures' [patent_app_type] => 1 [patent_app_number] => 8/083199 [patent_app_country] => US [patent_app_date] => 1993-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 44 [patent_no_of_words] => 13977 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315535.pdf [firstpage_image] =>[orig_patent_app_number] => 083199 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/083199
Automatic router capable of searching for a new wiring with reference to connection failures Jun 24, 1993 Issued
Array ( [id] => 3697108 [patent_doc_number] => 05644496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses' [patent_app_type] => 1 [patent_app_number] => 8/080658 [patent_app_country] => US [patent_app_date] => 1993-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 15745 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644496.pdf [firstpage_image] =>[orig_patent_app_number] => 080658 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/080658
Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses Jun 17, 1993 Issued
Array ( [id] => 3075834 [patent_doc_number] => 05353234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Computer aided designing system for designing a pattern for a printed circuit board' [patent_app_type] => 1 [patent_app_number] => 8/077494 [patent_app_country] => US [patent_app_date] => 1993-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3067 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/353/05353234.pdf [firstpage_image] =>[orig_patent_app_number] => 077494 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/077494
Computer aided designing system for designing a pattern for a printed circuit board Jun 16, 1993 Issued
08/078667 MULTIDIMENSIONAL SPECTRAL LOAD BALANCING Jun 15, 1993 Pending
Array ( [id] => 3435255 [patent_doc_number] => 05404311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Method of optimizing delay times' [patent_app_type] => 1 [patent_app_number] => 8/074840 [patent_app_country] => US [patent_app_date] => 1993-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6081 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404311.pdf [firstpage_image] =>[orig_patent_app_number] => 074840 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/074840
Method of optimizing delay times Jun 14, 1993 Issued
Array ( [id] => 3664095 [patent_doc_number] => 05623418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'System and method for creating and validating structural description of electronic system' [patent_app_type] => 1 [patent_app_number] => 8/077304 [patent_app_country] => US [patent_app_date] => 1993-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 49 [patent_no_of_words] => 27637 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623418.pdf [firstpage_image] =>[orig_patent_app_number] => 077304 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/077304
System and method for creating and validating structural description of electronic system Jun 13, 1993 Issued
Array ( [id] => 3596192 [patent_doc_number] => 05553002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface' [patent_app_type] => 1 [patent_app_number] => 8/077403 [patent_app_country] => US [patent_app_date] => 1993-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 26368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553002.pdf [firstpage_image] =>[orig_patent_app_number] => 077403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/077403
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface Jun 13, 1993 Issued
Array ( [id] => 3544128 [patent_doc_number] => 05557531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation' [patent_app_type] => 1 [patent_app_number] => 8/076738 [patent_app_country] => US [patent_app_date] => 1993-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 26362 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557531.pdf [firstpage_image] =>[orig_patent_app_number] => 076738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/076738
Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation Jun 13, 1993 Issued
Array ( [id] => 3565410 [patent_doc_number] => 05544067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation' [patent_app_type] => 1 [patent_app_number] => 8/077294 [patent_app_country] => US [patent_app_date] => 1993-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 19245 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544067.pdf [firstpage_image] =>[orig_patent_app_number] => 077294 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/077294
Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation Jun 13, 1993 Issued
Array ( [id] => 3536824 [patent_doc_number] => 05541849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters' [patent_app_type] => 1 [patent_app_number] => 8/076728 [patent_app_country] => US [patent_app_date] => 1993-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 26397 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541849.pdf [firstpage_image] =>[orig_patent_app_number] => 076728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/076728
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters Jun 13, 1993 Issued
Array ( [id] => 3565395 [patent_doc_number] => 05544066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints' [patent_app_type] => 1 [patent_app_number] => 8/076729 [patent_app_country] => US [patent_app_date] => 1993-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 26405 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544066.pdf [firstpage_image] =>[orig_patent_app_number] => 076729 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/076729
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints Jun 13, 1993 Issued
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