Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3435283 [patent_doc_number] => 05404313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'System for assigning positions of block terminals in a VLSI' [patent_app_type] => 1 [patent_app_number] => 8/037463 [patent_app_country] => US [patent_app_date] => 1993-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6397 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404313.pdf [firstpage_image] =>[orig_patent_app_number] => 037463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/037463
System for assigning positions of block terminals in a VLSI Mar 24, 1993 Issued
Array ( [id] => 3079715 [patent_doc_number] => 05361213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Control device for an automobile' [patent_app_type] => 1 [patent_app_number] => 8/037732 [patent_app_country] => US [patent_app_date] => 1993-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 66 [patent_no_of_words] => 8727 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361213.pdf [firstpage_image] =>[orig_patent_app_number] => 037732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/037732
Control device for an automobile Mar 23, 1993 Issued
08/033620 APPARATUS AND METHOD FOR TRACKING AND IDENTIFYING PRINTED CIRCUIT ASSEMBLIES Mar 18, 1993 Pending
Array ( [id] => 3003723 [patent_doc_number] => 05367461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Variably sensitive traction control method for vehicle' [patent_app_type] => 1 [patent_app_number] => 8/032544 [patent_app_country] => US [patent_app_date] => 1993-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4397 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367461.pdf [firstpage_image] =>[orig_patent_app_number] => 032544 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/032544
Variably sensitive traction control method for vehicle Mar 16, 1993 Issued
Array ( [id] => 3523172 [patent_doc_number] => 05513124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Logic placement using positionally asymmetrical partitioning method' [patent_app_type] => 1 [patent_app_number] => 8/030517 [patent_app_country] => US [patent_app_date] => 1993-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 11662 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513124.pdf [firstpage_image] =>[orig_patent_app_number] => 030517 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/030517
Logic placement using positionally asymmetrical partitioning method Mar 11, 1993 Issued
08/032830 METHOD AND APPARATUS FOR PROVIDING SHORTEST ELAPSED TIME ROUTE INFORMATION TO USERS Mar 9, 1993 Pending
Array ( [id] => 3497021 [patent_doc_number] => 05475606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Faraday cage for a printed circuit card' [patent_app_type] => 1 [patent_app_number] => 8/026888 [patent_app_country] => US [patent_app_date] => 1993-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4696 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475606.pdf [firstpage_image] =>[orig_patent_app_number] => 026888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/026888
Faraday cage for a printed circuit card Mar 4, 1993 Issued
Array ( [id] => 3008723 [patent_doc_number] => 05359536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Programmable gate array with improved interconnect structure, input/output structure and configurable logic block' [patent_app_type] => 1 [patent_app_number] => 8/025551 [patent_app_country] => US [patent_app_date] => 1993-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24983 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359536.pdf [firstpage_image] =>[orig_patent_app_number] => 025551 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/025551
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block Mar 2, 1993 Issued
Array ( [id] => 3489120 [patent_doc_number] => 05457638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Timing analysis of VLSI circuits' [patent_app_type] => 1 [patent_app_number] => 8/023828 [patent_app_country] => US [patent_app_date] => 1993-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4675 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457638.pdf [firstpage_image] =>[orig_patent_app_number] => 023828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023828
Timing analysis of VLSI circuits Feb 22, 1993 Issued
Array ( [id] => 3485112 [patent_doc_number] => 05432707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Automated circuit design' [patent_app_type] => 1 [patent_app_number] => 8/016619 [patent_app_country] => US [patent_app_date] => 1993-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2810 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432707.pdf [firstpage_image] =>[orig_patent_app_number] => 016619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/016619
Automated circuit design Feb 11, 1993 Issued
Array ( [id] => 3124357 [patent_doc_number] => 05396435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Automated circuit design system and method for reducing critical path delay times' [patent_app_type] => 1 [patent_app_number] => 8/016113 [patent_app_country] => US [patent_app_date] => 1993-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5085 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396435.pdf [firstpage_image] =>[orig_patent_app_number] => 016113 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/016113
Automated circuit design system and method for reducing critical path delay times Feb 9, 1993 Issued
Array ( [id] => 3432442 [patent_doc_number] => 05459672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Electrical interconnect integrity measuring method' [patent_app_type] => 1 [patent_app_number] => 8/015271 [patent_app_country] => US [patent_app_date] => 1993-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2914 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459672.pdf [firstpage_image] =>[orig_patent_app_number] => 015271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/015271
Electrical interconnect integrity measuring method Feb 4, 1993 Issued
Array ( [id] => 3043845 [patent_doc_number] => 05329460 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Programmable gate array with improved interconnect structure, input/output structure and configurable logic block' [patent_app_type] => 1 [patent_app_number] => 8/012573 [patent_app_country] => US [patent_app_date] => 1993-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24999 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329460.pdf [firstpage_image] =>[orig_patent_app_number] => 012573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/012573
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block Jan 31, 1993 Issued
Array ( [id] => 3530195 [patent_doc_number] => 05490095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method of extracting parameters for circuit simulation' [patent_app_type] => 1 [patent_app_number] => 8/005821 [patent_app_country] => US [patent_app_date] => 1993-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3037 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490095.pdf [firstpage_image] =>[orig_patent_app_number] => 005821 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/005821
Method of extracting parameters for circuit simulation Jan 18, 1993 Issued
08/001396 METHOD OF FORMING PATTERN HAVING OPTIONAL ANGLE IN CHARGED PARTICLE EXPOSURE SYSTEM Jan 5, 1993 Abandoned
Array ( [id] => 3877667 [patent_doc_number] => RE036189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Apparatus for reducing computer system power consumption' [patent_app_type] => 2 [patent_app_number] => 7/993093 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11457 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 79 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036189.pdf [firstpage_image] =>[orig_patent_app_number] => 993093 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993093
Apparatus for reducing computer system power consumption Dec 17, 1992 Issued
Array ( [id] => 3549199 [patent_doc_number] => 05481471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Mixed signal integrated circuit architecture and test methodology' [patent_app_type] => 1 [patent_app_number] => 7/993268 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4076 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481471.pdf [firstpage_image] =>[orig_patent_app_number] => 993268 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993268
Mixed signal integrated circuit architecture and test methodology Dec 17, 1992 Issued
Array ( [id] => 3122429 [patent_doc_number] => 05414638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Programmable interconnect architecture' [patent_app_type] => 1 [patent_app_number] => 7/993331 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4512 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414638.pdf [firstpage_image] =>[orig_patent_app_number] => 993331 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993331
Programmable interconnect architecture Dec 17, 1992 Issued
Array ( [id] => 3566430 [patent_doc_number] => 05502643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Method of and an apparatus for setting up parameters which are used to manufacture a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/991362 [patent_app_country] => US [patent_app_date] => 1992-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3968 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502643.pdf [firstpage_image] =>[orig_patent_app_number] => 991362 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/991362
Method of and an apparatus for setting up parameters which are used to manufacture a semiconductor device Dec 14, 1992 Issued
07/989928 METHOD AND APPARATUS FOR OPTIMIZING BLOCK SHAPE IN HIERARCHICAL IC DESIGN Dec 10, 1992 Abandoned
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