| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_issue_date] => 1995-04-04
[patent_title] => 'System for assigning positions of block terminals in a VLSI'
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[patent_app_number] => 8/037463
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Array
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[id] => 3079715
[patent_doc_number] => 05361213
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-01
[patent_title] => 'Control device for an automobile'
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[patent_app_date] => 1993-03-24
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[firstpage_image] =>[orig_patent_app_number] => 037732
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/037732 | Control device for an automobile | Mar 23, 1993 | Issued |
| 08/033620 | APPARATUS AND METHOD FOR TRACKING AND IDENTIFYING PRINTED CIRCUIT ASSEMBLIES | Mar 18, 1993 | Pending |
Array
(
[id] => 3003723
[patent_doc_number] => 05367461
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-22
[patent_title] => 'Variably sensitive traction control method for vehicle'
[patent_app_type] => 1
[patent_app_number] => 8/032544
[patent_app_country] => US
[patent_app_date] => 1993-03-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/032544 | Variably sensitive traction control method for vehicle | Mar 16, 1993 | Issued |
Array
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[id] => 3523172
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Logic placement using positionally asymmetrical partitioning method'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1993-03-12
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[firstpage_image] =>[orig_patent_app_number] => 030517
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/030517 | Logic placement using positionally asymmetrical partitioning method | Mar 11, 1993 | Issued |
| 08/032830 | METHOD AND APPARATUS FOR PROVIDING SHORTEST ELAPSED TIME ROUTE INFORMATION TO USERS | Mar 9, 1993 | Pending |
Array
(
[id] => 3497021
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[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Faraday cage for a printed circuit card'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/026888 | Faraday cage for a printed circuit card | Mar 4, 1993 | Issued |
Array
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[patent_kind] => NA
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Array
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[firstpage_image] =>[orig_patent_app_number] => 023828
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/023828 | Timing analysis of VLSI circuits | Feb 22, 1993 | Issued |
Array
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[id] => 3485112
[patent_doc_number] => 05432707
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[patent_kind] => NA
[patent_issue_date] => 1995-07-11
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[firstpage_image] =>[orig_patent_app_number] => 016619
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/016619 | Automated circuit design | Feb 11, 1993 | Issued |
Array
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[id] => 3124357
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[patent_kind] => NA
[patent_issue_date] => 1995-03-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/016113 | Automated circuit design system and method for reducing critical path delay times | Feb 9, 1993 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/015271 | Electrical interconnect integrity measuring method | Feb 4, 1993 | Issued |
Array
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Array
(
[id] => 3530195
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/005821 | Method of extracting parameters for circuit simulation | Jan 18, 1993 | Issued |
| 08/001396 | METHOD OF FORMING PATTERN HAVING OPTIONAL ANGLE IN CHARGED PARTICLE EXPOSURE SYSTEM | Jan 5, 1993 | Abandoned |
Array
(
[id] => 3877667
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/993093 | Apparatus for reducing computer system power consumption | Dec 17, 1992 | Issued |
Array
(
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Array
(
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Array
(
[id] => 3566430
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/991362 | Method of and an apparatus for setting up parameters which are used to manufacture a semiconductor device | Dec 14, 1992 | Issued |
| 07/989928 | METHOD AND APPARATUS FOR OPTIMIZING BLOCK SHAPE IN HIERARCHICAL IC DESIGN | Dec 10, 1992 | Abandoned |