Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3939488 [patent_doc_number] => 05877964 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Semiconductor device compensation system and method' [patent_app_type] => 1 [patent_app_number] => 8/781401 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5049 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877964.pdf [firstpage_image] =>[orig_patent_app_number] => 781401 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781401
Semiconductor device compensation system and method Jan 9, 1997 Issued
Array ( [id] => 3980208 [patent_doc_number] => 05886901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Flip-flop for scan test chain' [patent_app_type] => 1 [patent_app_number] => 8/779628 [patent_app_country] => US [patent_app_date] => 1997-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4047 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886901.pdf [firstpage_image] =>[orig_patent_app_number] => 779628 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779628
Flip-flop for scan test chain Jan 6, 1997 Issued
Array ( [id] => 3900451 [patent_doc_number] => 05749061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Clutch slip control device and method of manufacturing the same, clutch slip control method, and vehicle control device' [patent_app_type] => 1 [patent_app_number] => 8/778506 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 42 [patent_no_of_words] => 14304 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749061.pdf [firstpage_image] =>[orig_patent_app_number] => 778506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778506
Clutch slip control device and method of manufacturing the same, clutch slip control method, and vehicle control device Jan 2, 1997 Issued
Array ( [id] => 4010179 [patent_doc_number] => 05923565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Apparatus and method for extracting capacitance in the presence of two ground planes' [patent_app_type] => 1 [patent_app_number] => 8/778300 [patent_app_country] => US [patent_app_date] => 1997-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5946 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923565.pdf [firstpage_image] =>[orig_patent_app_number] => 778300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778300
Apparatus and method for extracting capacitance in the presence of two ground planes Jan 1, 1997 Issued
Array ( [id] => 3789356 [patent_doc_number] => 05757654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Reflective wave compensation on high speed processor cards' [patent_app_type] => 1 [patent_app_number] => 8/778319 [patent_app_country] => US [patent_app_date] => 1997-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 8192 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757654.pdf [firstpage_image] =>[orig_patent_app_number] => 778319 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778319
Reflective wave compensation on high speed processor cards Jan 1, 1997 Issued
Array ( [id] => 3797719 [patent_doc_number] => 05822227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Air-conditioning and ventilation simulator in subsurface space' [patent_app_type] => 1 [patent_app_number] => 8/771163 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9437 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822227.pdf [firstpage_image] =>[orig_patent_app_number] => 771163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/771163
Air-conditioning and ventilation simulator in subsurface space Dec 19, 1996 Issued
Array ( [id] => 3824176 [patent_doc_number] => 05812414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method for performing simulation using a hardware logic emulation system' [patent_app_type] => 1 [patent_app_number] => 8/770655 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 46992 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812414.pdf [firstpage_image] =>[orig_patent_app_number] => 770655 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770655
Method for performing simulation using a hardware logic emulation system Dec 18, 1996 Issued
Array ( [id] => 3872840 [patent_doc_number] => 05796623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Apparatus and method for performing computations with electrically reconfigurable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/770656 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 47039 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796623.pdf [firstpage_image] =>[orig_patent_app_number] => 770656 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770656
Apparatus and method for performing computations with electrically reconfigurable logic devices Dec 18, 1996 Issued
Array ( [id] => 3780320 [patent_doc_number] => 05734581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Method for implementing tri-state nets in a logic emulation system' [patent_app_type] => 1 [patent_app_number] => 8/769659 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 46989 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734581.pdf [firstpage_image] =>[orig_patent_app_number] => 769659 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769659
Method for implementing tri-state nets in a logic emulation system Dec 18, 1996 Issued
Array ( [id] => 3980279 [patent_doc_number] => 05886906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Method and apparatus of simulating semiconductor circuit' [patent_app_type] => 1 [patent_app_number] => 8/768400 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10105 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886906.pdf [firstpage_image] =>[orig_patent_app_number] => 768400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768400
Method and apparatus of simulating semiconductor circuit Dec 17, 1996 Issued
Array ( [id] => 3939541 [patent_doc_number] => 05877968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method for automotive vehicle body shape design' [patent_app_type] => 1 [patent_app_number] => 8/763387 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3080 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877968.pdf [firstpage_image] =>[orig_patent_app_number] => 763387 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763387
Method for automotive vehicle body shape design Dec 15, 1996 Issued
Array ( [id] => 4060835 [patent_doc_number] => 05870316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Methods of using simultaneous test verification software' [patent_app_type] => 1 [patent_app_number] => 8/761285 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2859 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870316.pdf [firstpage_image] =>[orig_patent_app_number] => 761285 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761285
Methods of using simultaneous test verification software Dec 5, 1996 Issued
Array ( [id] => 4026767 [patent_doc_number] => 05880975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method of producing simplified code from a circuit compiler' [patent_app_type] => 1 [patent_app_number] => 8/760744 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10722 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880975.pdf [firstpage_image] =>[orig_patent_app_number] => 760744 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760744
Method of producing simplified code from a circuit compiler Dec 4, 1996 Issued
Array ( [id] => 3993593 [patent_doc_number] => 05910900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Method of producing cache optimized code from a circuit compiler' [patent_app_type] => 1 [patent_app_number] => 8/759585 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10689 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910900.pdf [firstpage_image] =>[orig_patent_app_number] => 759585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759585
Method of producing cache optimized code from a circuit compiler Dec 4, 1996 Issued
Array ( [id] => 3980265 [patent_doc_number] => 05886905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Method of determining operating conditions for a nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/753786 [patent_app_country] => US [patent_app_date] => 1996-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6115 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886905.pdf [firstpage_image] =>[orig_patent_app_number] => 753786 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753786
Method of determining operating conditions for a nonvolatile semiconductor memory Dec 1, 1996 Issued
Array ( [id] => 3889134 [patent_doc_number] => 05825673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Device, method, and software products for extracting circuit-simulation parameters' [patent_app_type] => 1 [patent_app_number] => 8/756572 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5282 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825673.pdf [firstpage_image] =>[orig_patent_app_number] => 756572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756572
Device, method, and software products for extracting circuit-simulation parameters Nov 25, 1996 Issued
Array ( [id] => 4054226 [patent_doc_number] => 05875113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Process to prevent the exploitation of illicit knowledge of the structure or function of an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/746307 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2675 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875113.pdf [firstpage_image] =>[orig_patent_app_number] => 746307 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746307
Process to prevent the exploitation of illicit knowledge of the structure or function of an integrated circuit Nov 7, 1996 Issued
Array ( [id] => 4064026 [patent_doc_number] => 05933356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models' [patent_app_type] => 1 [patent_app_number] => 8/740967 [patent_app_country] => US [patent_app_date] => 1996-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 16832 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933356.pdf [firstpage_image] =>[orig_patent_app_number] => 740967 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/740967
Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models Nov 4, 1996 Issued
Array ( [id] => 3897627 [patent_doc_number] => 05805865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/721390 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7520 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805865.pdf [firstpage_image] =>[orig_patent_app_number] => 721390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721390
Semiconductor device Sep 25, 1996 Issued
Array ( [id] => 3756186 [patent_doc_number] => 05801958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information' [patent_app_type] => 1 [patent_app_number] => 8/707918 [patent_app_country] => US [patent_app_date] => 1996-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 65 [patent_no_of_words] => 47320 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801958.pdf [firstpage_image] =>[orig_patent_app_number] => 707918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707918
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information Sep 9, 1996 Issued
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