| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3055013
[patent_doc_number] => 05287282
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Misfire diagnosis apparatus for an internal combustion engine'
[patent_app_type] => 1
[patent_app_number] => 7/720388
[patent_app_country] => US
[patent_app_date] => 1991-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 7212
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 499
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/287/05287282.pdf
[firstpage_image] =>[orig_patent_app_number] => 720388
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/720388 | Misfire diagnosis apparatus for an internal combustion engine | Jun 24, 1991 | Issued |
Array
(
[id] => 3111128
[patent_doc_number] => 05315534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-24
[patent_title] => 'Computer process for interconnecting logic circuits utilizing softwire statements'
[patent_app_type] => 1
[patent_app_number] => 7/720356
[patent_app_country] => US
[patent_app_date] => 1991-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3262
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/315/05315534.pdf
[firstpage_image] =>[orig_patent_app_number] => 720356
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/720356 | Computer process for interconnecting logic circuits utilizing softwire statements | Jun 24, 1991 | Issued |
| 07/720093 | LAYOUT METHOD FOR A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE | Jun 23, 1991 | Abandoned |
Array
(
[id] => 3107067
[patent_doc_number] => 05299139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-29
[patent_title] => 'Short locator method'
[patent_app_type] => 1
[patent_app_number] => 7/718969
[patent_app_country] => US
[patent_app_date] => 1991-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 36
[patent_no_of_words] => 9793
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/299/05299139.pdf
[firstpage_image] =>[orig_patent_app_number] => 718969
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/718969 | Short locator method | Jun 20, 1991 | Issued |
Array
(
[id] => 3105309
[patent_doc_number] => 05293327
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Method of logic circuit simulation'
[patent_app_type] => 1
[patent_app_number] => 7/718686
[patent_app_country] => US
[patent_app_date] => 1991-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 2890
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/293/05293327.pdf
[firstpage_image] =>[orig_patent_app_number] => 718686
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/718686 | Method of logic circuit simulation | Jun 20, 1991 | Issued |
Array
(
[id] => 3457944
[patent_doc_number] => 05386374
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'Method for simulating the surface contours of a layer material to be formed over a base structure'
[patent_app_type] => 1
[patent_app_number] => 7/717148
[patent_app_country] => US
[patent_app_date] => 1991-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4319
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/386/05386374.pdf
[firstpage_image] =>[orig_patent_app_number] => 717148
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/717148 | Method for simulating the surface contours of a layer material to be formed over a base structure | Jun 17, 1991 | Issued |
Array
(
[id] => 3018729
[patent_doc_number] => 05331568
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-19
[patent_title] => 'Apparatus and method for determining sequential hardware equivalence'
[patent_app_type] => 1
[patent_app_number] => 7/717213
[patent_app_country] => US
[patent_app_date] => 1991-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 15878
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/331/05331568.pdf
[firstpage_image] =>[orig_patent_app_number] => 717213
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/717213 | Apparatus and method for determining sequential hardware equivalence | Jun 17, 1991 | Issued |
Array
(
[id] => 3467040
[patent_doc_number] => 05473546
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-05
[patent_title] => 'Method for flattening hierarchical design descriptions'
[patent_app_type] => 1
[patent_app_number] => 7/715114
[patent_app_country] => US
[patent_app_date] => 1991-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 13861
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/473/05473546.pdf
[firstpage_image] =>[orig_patent_app_number] => 715114
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/715114 | Method for flattening hierarchical design descriptions | Jun 11, 1991 | Issued |
Array
(
[id] => 3470529
[patent_doc_number] => 05392221
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Procedure to minimize total power of a logic network subject to timing constraints'
[patent_app_type] => 1
[patent_app_number] => 7/714027
[patent_app_country] => US
[patent_app_date] => 1991-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 7754
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/392/05392221.pdf
[firstpage_image] =>[orig_patent_app_number] => 714027
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/714027 | Procedure to minimize total power of a logic network subject to timing constraints | Jun 11, 1991 | Issued |
Array
(
[id] => 3005994
[patent_doc_number] => 05363302
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-08
[patent_title] => 'Power rate system and method for actuating vehicle safety device'
[patent_app_type] => 1
[patent_app_number] => 7/709891
[patent_app_country] => US
[patent_app_date] => 1991-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3619
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/363/05363302.pdf
[firstpage_image] =>[orig_patent_app_number] => 709891
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/709891 | Power rate system and method for actuating vehicle safety device | Jun 3, 1991 | Issued |
Array
(
[id] => 3074871
[patent_doc_number] => 05295082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-15
[patent_title] => 'Efficient method for multichip module interconnect'
[patent_app_type] => 1
[patent_app_number] => 7/708055
[patent_app_country] => US
[patent_app_date] => 1991-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 9595
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/295/05295082.pdf
[firstpage_image] =>[orig_patent_app_number] => 708055
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/708055 | Efficient method for multichip module interconnect | May 29, 1991 | Issued |
Array
(
[id] => 2944690
[patent_doc_number] => 05247455
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-21
[patent_title] => 'Method of verifying wiring layout'
[patent_app_type] => 1
[patent_app_number] => 7/707020
[patent_app_country] => US
[patent_app_date] => 1991-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 8889
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 290
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/247/05247455.pdf
[firstpage_image] =>[orig_patent_app_number] => 707020
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/707020 | Method of verifying wiring layout | May 28, 1991 | Issued |
Array
(
[id] => 3504193
[patent_doc_number] => 05508922
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'Flight recorders with static electronics memory'
[patent_app_type] => 1
[patent_app_number] => 7/706766
[patent_app_country] => US
[patent_app_date] => 1991-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5399
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/508/05508922.pdf
[firstpage_image] =>[orig_patent_app_number] => 706766
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/706766 | Flight recorders with static electronics memory | May 28, 1991 | Issued |
Array
(
[id] => 2903911
[patent_doc_number] => 05272645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-21
[patent_title] => 'Channel routing method'
[patent_app_type] => 1
[patent_app_number] => 7/704181
[patent_app_country] => US
[patent_app_date] => 1991-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5488
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 326
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/272/05272645.pdf
[firstpage_image] =>[orig_patent_app_number] => 704181
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/704181 | Channel routing method | May 21, 1991 | Issued |
| 07/703707 | DATA BASE ACCESS MECHANISM FOR RULES UTILIZED BY A SYNTHESIS PROCEDURE FOR LOGIC CIRCUIT DESIGN | May 20, 1991 | Abandoned |
Array
(
[id] => 3463679
[patent_doc_number] => 05452226
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-19
[patent_title] => 'Rule structure for insertion of new elements in a circuit design synthesis procedure'
[patent_app_type] => 1
[patent_app_number] => 7/703706
[patent_app_country] => US
[patent_app_date] => 1991-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5152
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/452/05452226.pdf
[firstpage_image] =>[orig_patent_app_number] => 703706
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/703706 | Rule structure for insertion of new elements in a circuit design synthesis procedure | May 20, 1991 | Issued |
Array
(
[id] => 2840338
[patent_doc_number] => 05175696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-29
[patent_title] => 'Rule structure in a procedure for synthesis of logic circuits'
[patent_app_type] => 1
[patent_app_number] => 7/703705
[patent_app_country] => US
[patent_app_date] => 1991-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4659
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/175/05175696.pdf
[firstpage_image] =>[orig_patent_app_number] => 703705
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/703705 | Rule structure in a procedure for synthesis of logic circuits | May 20, 1991 | Issued |
Array
(
[id] => 3025055
[patent_doc_number] => 05341308
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-23
[patent_title] => 'Methods for allocating circuit elements between circuit groups'
[patent_app_type] => 1
[patent_app_number] => 7/702001
[patent_app_country] => US
[patent_app_date] => 1991-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4393
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/341/05341308.pdf
[firstpage_image] =>[orig_patent_app_number] => 702001
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/702001 | Methods for allocating circuit elements between circuit groups | May 16, 1991 | Issued |
| 07/701509 | AUTOMATIC LATERAL GUIDANCE CONTROL SYSTEM | May 15, 1991 | Abandoned |
| 07/698734 | RECONFIGURABLE LOGIC BOARD | May 9, 1991 | Abandoned |