Vincent N. Trans

Array ( [id] => 3020681 [patent_doc_number] => 05282148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-25 [patent_title] => 'Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic' [patent_app_type] => 1 [patent_app_number] => 7/356023 [patent_app_country] => US [patent_app_date] => 1989-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5985 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/282/05282148.pdf [firstpage_image] =>[orig_patent_app_number] => 356023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2927974 [patent_doc_number] => 05193060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Method of hold-speed control during an upshift' [patent_app_type] => 1 [patent_app_number] => 7/351895 [patent_app_country] => US [patent_app_date] => 1989-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1815 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193060.pdf [firstpage_image] =>[orig_patent_app_number] => 351895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2755144 [patent_doc_number] => 05012421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Vehicle control apparatus' [patent_app_type] => 1 [patent_app_number] => 7/344526 [patent_app_country] => US [patent_app_date] => 1989-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3237 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/012/05012421.pdf [firstpage_image] =>[orig_patent_app_number] => 344526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2646027 [patent_doc_number] => 04910679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-20 [patent_title] => 'Step-and-repeat alignment and exposure method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/337654 [patent_app_country] => US [patent_app_date] => 1989-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8345 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/910/04910679.pdf [firstpage_image] =>[orig_patent_app_number] => 337654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2703393 [patent_doc_number] => 05065335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-12 [patent_title] => 'Decoding type select logic generating method' [patent_app_type] => 1 [patent_app_number] => 7/323968 [patent_app_country] => US [patent_app_date] => 1989-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6930 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/065/05065335.pdf [firstpage_image] =>[orig_patent_app_number] => 323968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2637150 [patent_doc_number] => 04907165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-06 [patent_title] => 'Electric energy measuring method' [patent_app_type] => 1 [patent_app_number] => 7/323254 [patent_app_country] => US [patent_app_date] => 1989-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2317 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/907/04907165.pdf [firstpage_image] =>[orig_patent_app_number] => 323254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2716900 [patent_doc_number] => 05062054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Layout pattern generation and geometric processing system for LSI circuits' [patent_app_type] => 1 [patent_app_number] => 7/322322 [patent_app_country] => US [patent_app_date] => 1989-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 5640 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/062/05062054.pdf [firstpage_image] =>[orig_patent_app_number] => 322322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2483669 [patent_doc_number] => 04890242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-26 [patent_title] => 'Solid-modeling system using topology directed subdivision for determination of surface intersections' [patent_app_type] => 1 [patent_app_number] => 7/308975 [patent_app_country] => US [patent_app_date] => 1989-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 15939 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/890/04890242.pdf [firstpage_image] =>[orig_patent_app_number] => 308975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2755262 [patent_doc_number] => 05012427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Semiconductor integrated circuit and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 7/303261 [patent_app_country] => US [patent_app_date] => 1989-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3739 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/012/05012427.pdf [firstpage_image] =>[orig_patent_app_number] => 303261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2641348 [patent_doc_number] => 04937756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-26 [patent_title] => 'Gated isolated structure' [patent_app_type] => 1 [patent_app_number] => 7/300582 [patent_app_country] => US [patent_app_date] => 1989-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 2794 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/937/04937756.pdf [firstpage_image] =>[orig_patent_app_number] => 300582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2688973 [patent_doc_number] => 05067091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-19 [patent_title] => 'Circuit design conversion apparatus' [patent_app_type] => 1 [patent_app_number] => 7/298909 [patent_app_country] => US [patent_app_date] => 1989-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 4339 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/067/05067091.pdf [firstpage_image] =>[orig_patent_app_number] => 298909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2823144 [patent_doc_number] => 05079717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-07 [patent_title] => 'Method and system for compaction-processing mask pattern data of a semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/299475 [patent_app_country] => US [patent_app_date] => 1989-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2295 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/079/05079717.pdf [firstpage_image] =>[orig_patent_app_number] => 299475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2928521 [patent_doc_number] => 05206815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Method for arranging modules in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/297476 [patent_app_country] => US [patent_app_date] => 1989-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2519 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206815.pdf [firstpage_image] =>[orig_patent_app_number] => 297476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2611609 [patent_doc_number] => 04931959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-05 [patent_title] => 'Optical shuffle arrangement' [patent_app_type] => 1 [patent_app_number] => 7/296284 [patent_app_country] => US [patent_app_date] => 1989-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4256 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/931/04931959.pdf [firstpage_image] =>[orig_patent_app_number] => 296284 [rel_patent_id] =>[rel_patent_doc_number] =>)