Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3635963 [patent_doc_number] => 05621651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Emulation devices, systems and methods with distributed control of test interfaces in clock domains' [patent_app_type] => 1 [patent_app_number] => 8/643703 [patent_app_country] => US [patent_app_date] => 1996-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 94 [patent_no_of_words] => 37621 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621651.pdf [firstpage_image] =>[orig_patent_app_number] => 643703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643703
Emulation devices, systems and methods with distributed control of test interfaces in clock domains May 5, 1996 Issued
Array ( [id] => 3840925 [patent_doc_number] => 05712792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Logic circuit sythesizing method utilizing binary decision diagram explored based upon hierarchy of correlation between input variables' [patent_app_type] => 1 [patent_app_number] => 8/633486 [patent_app_country] => US [patent_app_date] => 1996-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 10373 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712792.pdf [firstpage_image] =>[orig_patent_app_number] => 633486 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/633486
Logic circuit sythesizing method utilizing binary decision diagram explored based upon hierarchy of correlation between input variables Apr 16, 1996 Issued
Array ( [id] => 3741484 [patent_doc_number] => 05694328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Method for designing a large scale integrated (LSI) layout' [patent_app_type] => 1 [patent_app_number] => 8/631904 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 2649 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694328.pdf [firstpage_image] =>[orig_patent_app_number] => 631904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/631904
Method for designing a large scale integrated (LSI) layout Apr 11, 1996 Issued
Array ( [id] => 3751661 [patent_doc_number] => 05787008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Simulation corrected sensitivity' [patent_app_type] => 1 [patent_app_number] => 8/629488 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 8269 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787008.pdf [firstpage_image] =>[orig_patent_app_number] => 629488 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/629488
Simulation corrected sensitivity Apr 9, 1996 Issued
Array ( [id] => 3912220 [patent_doc_number] => 05751593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Accurate delay prediction based on multi-model analysis' [patent_app_type] => 1 [patent_app_number] => 8/629487 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 8310 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751593.pdf [firstpage_image] =>[orig_patent_app_number] => 629487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/629487
Accurate delay prediction based on multi-model analysis Apr 9, 1996 Issued
Array ( [id] => 3829868 [patent_doc_number] => 05790415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Complementary network reduction for load modeling' [patent_app_type] => 1 [patent_app_number] => 8/630189 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 8295 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790415.pdf [firstpage_image] =>[orig_patent_app_number] => 630189 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630189
Complementary network reduction for load modeling Apr 9, 1996 Issued
Array ( [id] => 3712322 [patent_doc_number] => 05675499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Optimal probe point placement' [patent_app_type] => 1 [patent_app_number] => 8/626484 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 36 [patent_no_of_words] => 9646 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675499.pdf [firstpage_image] =>[orig_patent_app_number] => 626484 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626484
Optimal probe point placement Apr 1, 1996 Issued
Array ( [id] => 4068071 [patent_doc_number] => 05933620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method and apparatus for serializing microprocessor identification numbers' [patent_app_type] => 1 [patent_app_number] => 8/623022 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933620.pdf [firstpage_image] =>[orig_patent_app_number] => 623022 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623022
Method and apparatus for serializing microprocessor identification numbers Mar 27, 1996 Issued
Array ( [id] => 3939514 [patent_doc_number] => 05877966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'System and method for creating configurations using templates' [patent_app_type] => 1 [patent_app_number] => 8/617375 [patent_app_country] => US [patent_app_date] => 1996-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 7792 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877966.pdf [firstpage_image] =>[orig_patent_app_number] => 617375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/617375
System and method for creating configurations using templates Mar 17, 1996 Issued
Array ( [id] => 3888082 [patent_doc_number] => 05764531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Sizing apparatus for active devices of integrated circuits and sizing method therefor' [patent_app_type] => 1 [patent_app_number] => 8/616991 [patent_app_country] => US [patent_app_date] => 1996-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6770 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764531.pdf [firstpage_image] =>[orig_patent_app_number] => 616991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616991
Sizing apparatus for active devices of integrated circuits and sizing method therefor Mar 13, 1996 Issued
Array ( [id] => 3789419 [patent_doc_number] => 05757658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Procedure and system for placement optimization of cells within circuit blocks by optimizing placement of input/output ports within an integrated circuit design' [patent_app_type] => 1 [patent_app_number] => 8/611785 [patent_app_country] => US [patent_app_date] => 1996-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6660 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757658.pdf [firstpage_image] =>[orig_patent_app_number] => 611785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611785
Procedure and system for placement optimization of cells within circuit blocks by optimizing placement of input/output ports within an integrated circuit design Mar 5, 1996 Issued
Array ( [id] => 3918731 [patent_doc_number] => 05752006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Configuration emulation of a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/613785 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7077 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752006.pdf [firstpage_image] =>[orig_patent_app_number] => 613785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/613785
Configuration emulation of a programmable logic device Feb 28, 1996 Issued
08/607434 ECAD SYSTEM FOR DERIVING EXECUTABLE LOW-LEVEL STRUCTURAL DESCRIPTIONS AND VALID PHYSICAL IMPLEMENTATIONS OF CIRCUITS AND SYSTEMS FROM HIGH-LEVEL SEMANTIC DESCRIPTIONS THEREOF Feb 26, 1996 Abandoned
08/603037 SPECIFICATION AND DESIGN OF COMPLEX DIGITAL SYSTEMS Feb 15, 1996 Abandoned
Array ( [id] => 3673597 [patent_doc_number] => 05598346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks' [patent_app_type] => 1 [patent_app_number] => 8/596679 [patent_app_country] => US [patent_app_date] => 1996-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24987 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598346.pdf [firstpage_image] =>[orig_patent_app_number] => 596679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/596679
Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks Feb 4, 1996 Issued
Array ( [id] => 3751648 [patent_doc_number] => 05787007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Structure and method for loading RAM data within a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/593985 [patent_app_country] => US [patent_app_date] => 1996-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3555 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787007.pdf [firstpage_image] =>[orig_patent_app_number] => 593985 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/593985
Structure and method for loading RAM data within a programmable logic device Jan 29, 1996 Issued
Array ( [id] => 3751734 [patent_doc_number] => 05787013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Automatic routing method for inter-functional cells' [patent_app_type] => 1 [patent_app_number] => 8/593526 [patent_app_country] => US [patent_app_date] => 1996-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 37 [patent_no_of_words] => 3429 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787013.pdf [firstpage_image] =>[orig_patent_app_number] => 593526 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/593526
Automatic routing method for inter-functional cells Jan 29, 1996 Issued
08/593595 ONBOARD NAVIGATIONAL SYSTEM Jan 28, 1996 Abandoned
Array ( [id] => 3557727 [patent_doc_number] => 05546320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Method for performing integrated section-level and full-chip timing verification for custom microprocessor designs' [patent_app_type] => 1 [patent_app_number] => 8/588161 [patent_app_country] => US [patent_app_date] => 1996-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2572 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546320.pdf [firstpage_image] =>[orig_patent_app_number] => 588161 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/588161
Method for performing integrated section-level and full-chip timing verification for custom microprocessor designs Jan 17, 1996 Issued
Array ( [id] => 3559056 [patent_doc_number] => 05548525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Method and apparatus for pin assignment in automatic circuit testers' [patent_app_type] => 1 [patent_app_number] => 8/580795 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3649 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548525.pdf [firstpage_image] =>[orig_patent_app_number] => 580795 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/580795
Method and apparatus for pin assignment in automatic circuit testers Dec 28, 1995 Issued
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