Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3738683 [patent_doc_number] => 05703789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Test ready compiler for design for test synthesis' [patent_app_type] => 1 [patent_app_number] => 8/581187 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 15959 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703789.pdf [firstpage_image] =>[orig_patent_app_number] => 581187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581187
Test ready compiler for design for test synthesis Dec 28, 1995 Issued
Array ( [id] => 3830226 [patent_doc_number] => 05812822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Apparatus for coordinating clock oscillators in a fully redundant computer system' [patent_app_type] => 1 [patent_app_number] => 8/574821 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 33 [patent_no_of_words] => 4854 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 454 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812822.pdf [firstpage_image] =>[orig_patent_app_number] => 574821 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/574821
Apparatus for coordinating clock oscillators in a fully redundant computer system Dec 18, 1995 Issued
Array ( [id] => 3715505 [patent_doc_number] => 05654897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Method and structure for improving patterning design for processing' [patent_app_type] => 1 [patent_app_number] => 8/567288 [patent_app_country] => US [patent_app_date] => 1995-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3352 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654897.pdf [firstpage_image] =>[orig_patent_app_number] => 567288 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/567288
Method and structure for improving patterning design for processing Dec 4, 1995 Issued
Array ( [id] => 3808856 [patent_doc_number] => 05828578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield' [patent_app_type] => 1 [patent_app_number] => 8/564721 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6923 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828578.pdf [firstpage_image] =>[orig_patent_app_number] => 564721 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/564721
Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield Nov 28, 1995 Issued
Array ( [id] => 3630647 [patent_doc_number] => 05689433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Method and apparatus for compacting integrated circuits with wire length minimization' [patent_app_type] => 1 [patent_app_number] => 8/433438 [patent_app_country] => US [patent_app_date] => 1995-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 59 [patent_no_of_words] => 16079 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689433.pdf [firstpage_image] =>[orig_patent_app_number] => 433438 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/433438
Method and apparatus for compacting integrated circuits with wire length minimization Nov 27, 1995 Issued
Array ( [id] => 3822078 [patent_doc_number] => 05710710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Frequency counter with reduced false correlations' [patent_app_type] => 1 [patent_app_number] => 8/561692 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3930 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710710.pdf [firstpage_image] =>[orig_patent_app_number] => 561692 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/561692
Frequency counter with reduced false correlations Nov 21, 1995 Issued
Array ( [id] => 3518572 [patent_doc_number] => 05587921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer' [patent_app_type] => 1 [patent_app_number] => 8/560933 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24986 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587921.pdf [firstpage_image] =>[orig_patent_app_number] => 560933 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560933
Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer Nov 19, 1995 Issued
Array ( [id] => 3804929 [patent_doc_number] => 05822711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Autonomous controller for traffic signals' [patent_app_type] => 1 [patent_app_number] => 8/560163 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3732 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822711.pdf [firstpage_image] =>[orig_patent_app_number] => 560163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560163
Autonomous controller for traffic signals Nov 19, 1995 Issued
Array ( [id] => 4068710 [patent_doc_number] => 05970236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Circuit for selectively performing data format conversion' [patent_app_type] => 1 [patent_app_number] => 8/557487 [patent_app_country] => US [patent_app_date] => 1995-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5012 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970236.pdf [firstpage_image] =>[orig_patent_app_number] => 557487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/557487
Circuit for selectively performing data format conversion Nov 13, 1995 Issued
Array ( [id] => 3703924 [patent_doc_number] => 05680332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Measurement of digital circuit simulation test coverage utilizing BDDs and state bins' [patent_app_type] => 1 [patent_app_number] => 8/540686 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 13113 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680332.pdf [firstpage_image] =>[orig_patent_app_number] => 540686 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540686
Measurement of digital circuit simulation test coverage utilizing BDDs and state bins Oct 29, 1995 Issued
Array ( [id] => 3888017 [patent_doc_number] => 05764527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Optimizing method for logic circuit and logic circuit optimizing system' [patent_app_type] => 1 [patent_app_number] => 8/549548 [patent_app_country] => US [patent_app_date] => 1995-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 7628 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764527.pdf [firstpage_image] =>[orig_patent_app_number] => 549548 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/549548
Optimizing method for logic circuit and logic circuit optimizing system Oct 26, 1995 Issued
Array ( [id] => 3866306 [patent_doc_number] => 05768156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Connectivity-based, all-hexahedral mesh generation method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/548286 [patent_app_country] => US [patent_app_date] => 1995-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 79 [patent_no_of_words] => 28144 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768156.pdf [firstpage_image] =>[orig_patent_app_number] => 548286 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548286
Connectivity-based, all-hexahedral mesh generation method and apparatus Oct 24, 1995 Issued
Array ( [id] => 3843160 [patent_doc_number] => 05740067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method for clock skew cost calculation' [patent_app_type] => 1 [patent_app_number] => 8/547686 [patent_app_country] => US [patent_app_date] => 1995-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5018 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740067.pdf [firstpage_image] =>[orig_patent_app_number] => 547686 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/547686
Method for clock skew cost calculation Oct 18, 1995 Issued
Array ( [id] => 3738305 [patent_doc_number] => 05671167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method and apparatus for forming a model for use in finite element method analysis' [patent_app_type] => 1 [patent_app_number] => 8/540187 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 55 [patent_no_of_words] => 14616 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671167.pdf [firstpage_image] =>[orig_patent_app_number] => 540187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540187
Method and apparatus for forming a model for use in finite element method analysis Oct 5, 1995 Issued
Array ( [id] => 3767461 [patent_doc_number] => 05721879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Emulator dedicated one-chip microcomputer' [patent_app_type] => 1 [patent_app_number] => 8/537489 [patent_app_country] => US [patent_app_date] => 1995-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5661 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721879.pdf [firstpage_image] =>[orig_patent_app_number] => 537489 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/537489
Emulator dedicated one-chip microcomputer Oct 1, 1995 Issued
08/536399 SERVO LUNG SIMULATOR AND RELATED CONTROL METHOD Sep 28, 1995 Abandoned
Array ( [id] => 3867285 [patent_doc_number] => 05706205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Apparatus and method for high-level synthesis of a logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/534065 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706205.pdf [firstpage_image] =>[orig_patent_app_number] => 534065 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534065
Apparatus and method for high-level synthesis of a logic circuit Sep 25, 1995 Issued
Array ( [id] => 3783408 [patent_doc_number] => 05774370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method of extracting implicit sequential behavior from hardware description languages' [patent_app_type] => 1 [patent_app_number] => 8/531996 [patent_app_country] => US [patent_app_date] => 1995-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 6982 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774370.pdf [firstpage_image] =>[orig_patent_app_number] => 531996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/531996
Method of extracting implicit sequential behavior from hardware description languages Sep 17, 1995 Issued
Array ( [id] => 3703525 [patent_doc_number] => 05661671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Bending angle detecting position setting device' [patent_app_type] => 1 [patent_app_number] => 8/522116 [patent_app_country] => US [patent_app_date] => 1995-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 47 [patent_no_of_words] => 12025 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661671.pdf [firstpage_image] =>[orig_patent_app_number] => 522116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522116
Bending angle detecting position setting device Aug 30, 1995 Issued
Array ( [id] => 4077044 [patent_doc_number] => 05867396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method and apparatus for making incremental changes to an integrated circuit design' [patent_app_type] => 1 [patent_app_number] => 8/523070 [patent_app_country] => US [patent_app_date] => 1995-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6113 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867396.pdf [firstpage_image] =>[orig_patent_app_number] => 523070 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/523070
Method and apparatus for making incremental changes to an integrated circuit design Aug 30, 1995 Issued
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