
Vincent N. Trans
Examiner (ID: 10207)
| Most Active Art Unit | 2304 |
| Art Unit(s) | 2763, 2304, 2899, OPET, 2787 |
| Total Applications | 1054 |
| Issued Applications | 820 |
| Pending Applications | 21 |
| Abandoned Applications | 213 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3764725
[patent_doc_number] => 05721690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Logic circuit synthesis'
[patent_app_type] => 1
[patent_app_number] => 8/516549
[patent_app_country] => US
[patent_app_date] => 1995-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4125
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721690.pdf
[firstpage_image] =>[orig_patent_app_number] => 516549
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/516549 | Logic circuit synthesis | Aug 17, 1995 | Issued |
Array
(
[id] => 3671067
[patent_doc_number] => 05657243
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Method and apparatus for automatically arranging circuit elements in data-path circuit'
[patent_app_type] => 1
[patent_app_number] => 8/510673
[patent_app_country] => US
[patent_app_date] => 1995-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 5136
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/657/05657243.pdf
[firstpage_image] =>[orig_patent_app_number] => 510673
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/510673 | Method and apparatus for automatically arranging circuit elements in data-path circuit | Aug 2, 1995 | Issued |
Array
(
[id] => 3858157
[patent_doc_number] => 05719795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-17
[patent_title] => 'Method to provide consistent estimated growth and yield values for loblolly pine plantations'
[patent_app_type] => 1
[patent_app_number] => 8/507779
[patent_app_country] => US
[patent_app_date] => 1995-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 76
[patent_figures_cnt] => 76
[patent_no_of_words] => 28265
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/719/05719795.pdf
[firstpage_image] =>[orig_patent_app_number] => 507779
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/507779 | Method to provide consistent estimated growth and yield values for loblolly pine plantations | Jul 25, 1995 | Issued |
Array
(
[id] => 3752771
[patent_doc_number] => 05754442
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Path analyzing displaying apparatus for designing logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/505964
[patent_app_country] => US
[patent_app_date] => 1995-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 9391
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754442.pdf
[firstpage_image] =>[orig_patent_app_number] => 505964
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/505964 | Path analyzing displaying apparatus for designing logic circuit | Jul 23, 1995 | Issued |
Array
(
[id] => 3638438
[patent_doc_number] => 05687094
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Design verification apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/498764
[patent_app_country] => US
[patent_app_date] => 1995-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 4467
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/687/05687094.pdf
[firstpage_image] =>[orig_patent_app_number] => 498764
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/498764 | Design verification apparatus | Jul 5, 1995 | Issued |
Array
(
[id] => 3888098
[patent_doc_number] => 05764532
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Automated method and system for designing an optimized integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/498328
[patent_app_country] => US
[patent_app_date] => 1995-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3379
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 280
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764532.pdf
[firstpage_image] =>[orig_patent_app_number] => 498328
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/498328 | Automated method and system for designing an optimized integrated circuit | Jul 4, 1995 | Issued |
Array
(
[id] => 3843144
[patent_doc_number] => 05740066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Electrical circuit board and circuit board assembly'
[patent_app_type] => 1
[patent_app_number] => 8/497974
[patent_app_country] => US
[patent_app_date] => 1995-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 899
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/740/05740066.pdf
[firstpage_image] =>[orig_patent_app_number] => 497974
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/497974 | Electrical circuit board and circuit board assembly | Jul 2, 1995 | Issued |
Array
(
[id] => 3523095
[patent_doc_number] => 05513119
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Hierarchical floorplanner for gate array design layout'
[patent_app_type] => 1
[patent_app_number] => 8/493016
[patent_app_country] => US
[patent_app_date] => 1995-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 6068
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513119.pdf
[firstpage_image] =>[orig_patent_app_number] => 493016
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/493016 | Hierarchical floorplanner for gate array design layout | Jun 20, 1995 | Issued |
Array
(
[id] => 3706506
[patent_doc_number] => 05677856
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-14
[patent_title] => 'Simulation apparatus for circuit verification'
[patent_app_type] => 1
[patent_app_number] => 8/492793
[patent_app_country] => US
[patent_app_date] => 1995-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 27
[patent_no_of_words] => 12171
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/677/05677856.pdf
[firstpage_image] =>[orig_patent_app_number] => 492793
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/492793 | Simulation apparatus for circuit verification | Jun 19, 1995 | Issued |
Array
(
[id] => 3572331
[patent_doc_number] => 05526278
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-11
[patent_title] => 'Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations'
[patent_app_type] => 1
[patent_app_number] => 8/492604
[patent_app_country] => US
[patent_app_date] => 1995-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 31
[patent_no_of_words] => 7994
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 582
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/526/05526278.pdf
[firstpage_image] =>[orig_patent_app_number] => 492604
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/492604 | Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations | Jun 19, 1995 | Issued |
Array
(
[id] => 3888271
[patent_doc_number] => 05764543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Extensible model network representation system for process planning'
[patent_app_type] => 1
[patent_app_number] => 8/491153
[patent_app_country] => US
[patent_app_date] => 1995-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 5358
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764543.pdf
[firstpage_image] =>[orig_patent_app_number] => 491153
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/491153 | Extensible model network representation system for process planning | Jun 15, 1995 | Issued |
Array
(
[id] => 3741714
[patent_doc_number] => 05694344
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Method for electrically modeling a semiconductor package'
[patent_app_type] => 1
[patent_app_number] => 8/491195
[patent_app_country] => US
[patent_app_date] => 1995-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4021
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/694/05694344.pdf
[firstpage_image] =>[orig_patent_app_number] => 491195
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/491195 | Method for electrically modeling a semiconductor package | Jun 14, 1995 | Issued |
| 08/489598 | METHODS AND APPARATUS FOR PLANNING AND MANAGING A COMMUNICATIONS NETWORK | Jun 11, 1995 | Abandoned |
Array
(
[id] => 3808841
[patent_doc_number] => 05828577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Devices and systems with protective terminal configuration, and methods'
[patent_app_type] => 1
[patent_app_number] => 8/485265
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 44
[patent_no_of_words] => 28046
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/828/05828577.pdf
[firstpage_image] =>[orig_patent_app_number] => 485265
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/485265 | Devices and systems with protective terminal configuration, and methods | Jun 6, 1995 | Issued |
Array
(
[id] => 3747078
[patent_doc_number] => 05699283
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Logic emulation system'
[patent_app_type] => 1
[patent_app_number] => 8/483987
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 4372
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/699/05699283.pdf
[firstpage_image] =>[orig_patent_app_number] => 483987
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/483987 | Logic emulation system | Jun 6, 1995 | Issued |
Array
(
[id] => 3612228
[patent_doc_number] => 05579218
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Devices and systems with parallel logic unit, and methods'
[patent_app_type] => 1
[patent_app_number] => 8/485205
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 44
[patent_no_of_words] => 28000
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/579/05579218.pdf
[firstpage_image] =>[orig_patent_app_number] => 485205
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/485205 | Devices and systems with parallel logic unit, and methods | Jun 6, 1995 | Issued |
Array
(
[id] => 3900065
[patent_doc_number] => 05777885
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Devices and systems with protective terminal configuration, and methods'
[patent_app_type] => 1
[patent_app_number] => 8/484401
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 44
[patent_no_of_words] => 27954
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/777/05777885.pdf
[firstpage_image] =>[orig_patent_app_number] => 484401
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484401 | Devices and systems with protective terminal configuration, and methods | Jun 6, 1995 | Issued |
Array
(
[id] => 4170233
[patent_doc_number] => 06019496
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'System and method for relating disparate data models of physical objects'
[patent_app_type] => 1
[patent_app_number] => 8/475120
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3824
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/019/06019496.pdf
[firstpage_image] =>[orig_patent_app_number] => 475120
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/475120 | System and method for relating disparate data models of physical objects | Jun 6, 1995 | Issued |
Array
(
[id] => 3843227
[patent_doc_number] => 05740071
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Method and apparatus for selective shape adjustment of hierarchical designs'
[patent_app_type] => 1
[patent_app_number] => 8/487814
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2694
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/740/05740071.pdf
[firstpage_image] =>[orig_patent_app_number] => 487814
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/487814 | Method and apparatus for selective shape adjustment of hierarchical designs | Jun 6, 1995 | Issued |
Array
(
[id] => 3616474
[patent_doc_number] => 05579497
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Devices and systems with parallel logic unit, and methods'
[patent_app_type] => 1
[patent_app_number] => 8/484115
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 44
[patent_no_of_words] => 27940
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/579/05579497.pdf
[firstpage_image] =>[orig_patent_app_number] => 484115
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484115 | Devices and systems with parallel logic unit, and methods | Jun 6, 1995 | Issued |