Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3726977 [patent_doc_number] => 05617318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Dynamically reconfigurable data processing system' [patent_app_type] => 1 [patent_app_number] => 8/437293 [patent_app_country] => US [patent_app_date] => 1995-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2602 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617318.pdf [firstpage_image] =>[orig_patent_app_number] => 437293 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/437293
Dynamically reconfigurable data processing system May 7, 1995 Issued
Array ( [id] => 3853160 [patent_doc_number] => 05745372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Apparatus and method for routing signals in a field programmable gate array integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/434836 [patent_app_country] => US [patent_app_date] => 1995-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6156 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745372.pdf [firstpage_image] =>[orig_patent_app_number] => 434836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/434836
Apparatus and method for routing signals in a field programmable gate array integrated circuit May 3, 1995 Issued
Array ( [id] => 3897293 [patent_doc_number] => 05715170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Apparatus for forming input data for a logic simulator' [patent_app_type] => 1 [patent_app_number] => 8/424624 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7317 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715170.pdf [firstpage_image] =>[orig_patent_app_number] => 424624 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/424624
Apparatus for forming input data for a logic simulator Apr 18, 1995 Issued
Array ( [id] => 3529878 [patent_doc_number] => 05490074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Constant delay interconnect for coupling configurable logic blocks' [patent_app_type] => 1 [patent_app_number] => 8/423303 [patent_app_country] => US [patent_app_date] => 1995-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490074.pdf [firstpage_image] =>[orig_patent_app_number] => 423303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/423303
Constant delay interconnect for coupling configurable logic blocks Apr 17, 1995 Issued
Array ( [id] => 3840899 [patent_doc_number] => 05712790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Method of power reduction in pla\'s' [patent_app_type] => 1 [patent_app_number] => 8/419772 [patent_app_country] => US [patent_app_date] => 1995-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2971 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712790.pdf [firstpage_image] =>[orig_patent_app_number] => 419772 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/419772
Method of power reduction in pla's Apr 10, 1995 Issued
08/414574 SYSTEM FOR OPTIMIZING POWER NETWORK DESIGN RELIABILITY Mar 30, 1995 Abandoned
Array ( [id] => 3657585 [patent_doc_number] => 05638305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Vibration/noise control system' [patent_app_type] => 1 [patent_app_number] => 8/410273 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14820 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638305.pdf [firstpage_image] =>[orig_patent_app_number] => 410273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/410273
Vibration/noise control system Mar 23, 1995 Issued
Array ( [id] => 3564793 [patent_doc_number] => 05500808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-19 [patent_title] => 'Apparatus and method for estimating time delays using unmapped combinational logic networks' [patent_app_type] => 1 [patent_app_number] => 8/409627 [patent_app_country] => US [patent_app_date] => 1995-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12694 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/500/05500808.pdf [firstpage_image] =>[orig_patent_app_number] => 409627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/409627
Apparatus and method for estimating time delays using unmapped combinational logic networks Mar 22, 1995 Issued
Array ( [id] => 3656615 [patent_doc_number] => 05629858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'CMOS transistor network to gate level model extractor for simulation, verification and test generation' [patent_app_type] => 1 [patent_app_number] => 8/406283 [patent_app_country] => US [patent_app_date] => 1995-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1140 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629858.pdf [firstpage_image] =>[orig_patent_app_number] => 406283 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/406283
CMOS transistor network to gate level model extractor for simulation, verification and test generation Mar 16, 1995 Issued
Array ( [id] => 3733055 [patent_doc_number] => 05701246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Suspension control apparatus' [patent_app_type] => 1 [patent_app_number] => 8/405873 [patent_app_country] => US [patent_app_date] => 1995-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 44 [patent_no_of_words] => 15060 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701246.pdf [firstpage_image] =>[orig_patent_app_number] => 405873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/405873
Suspension control apparatus Mar 16, 1995 Issued
Array ( [id] => 3706281 [patent_doc_number] => 05677841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Control target surveillance system' [patent_app_type] => 1 [patent_app_number] => 8/401270 [patent_app_country] => US [patent_app_date] => 1995-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 13529 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677841.pdf [firstpage_image] =>[orig_patent_app_number] => 401270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/401270
Control target surveillance system Mar 8, 1995 Issued
Array ( [id] => 3756003 [patent_doc_number] => 05801943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Traffic surveillance and simulation apparatus' [patent_app_type] => 1 [patent_app_number] => 8/398770 [patent_app_country] => US [patent_app_date] => 1995-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 40 [patent_no_of_words] => 27693 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801943.pdf [firstpage_image] =>[orig_patent_app_number] => 398770 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/398770
Traffic surveillance and simulation apparatus Mar 5, 1995 Issued
Array ( [id] => 3891678 [patent_doc_number] => 05748487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'System and method for generating a hazard-free asynchronous circuit' [patent_app_type] => 1 [patent_app_number] => 8/381081 [patent_app_country] => US [patent_app_date] => 1995-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 41 [patent_no_of_words] => 17427 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748487.pdf [firstpage_image] =>[orig_patent_app_number] => 381081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/381081
System and method for generating a hazard-free asynchronous circuit Jan 30, 1995 Issued
Array ( [id] => 3549272 [patent_doc_number] => 05481476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Apparatus for interactive self-modeling mixture analysis' [patent_app_type] => 1 [patent_app_number] => 8/379829 [patent_app_country] => US [patent_app_date] => 1995-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 74 [patent_no_of_words] => 15355 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481476.pdf [firstpage_image] =>[orig_patent_app_number] => 379829 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/379829
Apparatus for interactive self-modeling mixture analysis Jan 26, 1995 Issued
Array ( [id] => 3702996 [patent_doc_number] => 05650947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Logic simulation method and logic simulator' [patent_app_type] => 1 [patent_app_number] => 8/377404 [patent_app_country] => US [patent_app_date] => 1995-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 9865 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650947.pdf [firstpage_image] =>[orig_patent_app_number] => 377404 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/377404
Logic simulation method and logic simulator Jan 23, 1995 Issued
Array ( [id] => 3418818 [patent_doc_number] => 05461574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Method of expressing a logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/373451 [patent_app_country] => US [patent_app_date] => 1995-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 49 [patent_no_of_words] => 6179 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/461/05461574.pdf [firstpage_image] =>[orig_patent_app_number] => 373451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/373451
Method of expressing a logic circuit Jan 16, 1995 Issued
Array ( [id] => 3671944 [patent_doc_number] => 05625564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'System and method for hierarchical device extraction' [patent_app_type] => 1 [patent_app_number] => 8/372316 [patent_app_country] => US [patent_app_date] => 1995-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4864 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625564.pdf [firstpage_image] =>[orig_patent_app_number] => 372316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/372316
System and method for hierarchical device extraction Jan 12, 1995 Issued
Array ( [id] => 3482035 [patent_doc_number] => 05477466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Method and structure for improving patterning design for processing' [patent_app_type] => 1 [patent_app_number] => 8/362839 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3361 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477466.pdf [firstpage_image] =>[orig_patent_app_number] => 362839 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/362839
Method and structure for improving patterning design for processing Dec 21, 1994 Issued
Array ( [id] => 3997797 [patent_doc_number] => 05959871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Programmable analog array circuit' [patent_app_type] => 1 [patent_app_number] => 8/362838 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 64 [patent_no_of_words] => 19446 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959871.pdf [firstpage_image] =>[orig_patent_app_number] => 362838 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/362838
Programmable analog array circuit Dec 21, 1994 Issued
Array ( [id] => 3701938 [patent_doc_number] => 05604892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Method for modeling a physical system of elements using a relational database' [patent_app_type] => 1 [patent_app_number] => 8/359335 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 36 [patent_no_of_words] => 7267 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604892.pdf [firstpage_image] =>[orig_patent_app_number] => 359335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359335
Method for modeling a physical system of elements using a relational database Dec 18, 1994 Issued
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