
Vincent N. Trans
Examiner (ID: 10207)
| Most Active Art Unit | 2304 |
| Art Unit(s) | 2763, 2304, 2899, OPET, 2787 |
| Total Applications | 1054 |
| Issued Applications | 820 |
| Pending Applications | 21 |
| Abandoned Applications | 213 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3726977
[patent_doc_number] => 05617318
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-01
[patent_title] => 'Dynamically reconfigurable data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/437293
[patent_app_country] => US
[patent_app_date] => 1995-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2602
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[pdf_file] => patents/05/617/05617318.pdf
[firstpage_image] =>[orig_patent_app_number] => 437293
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/437293 | Dynamically reconfigurable data processing system | May 7, 1995 | Issued |
Array
(
[id] => 3853160
[patent_doc_number] => 05745372
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Apparatus and method for routing signals in a field programmable gate array integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/434836
[patent_app_country] => US
[patent_app_date] => 1995-05-04
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[pdf_file] => patents/05/745/05745372.pdf
[firstpage_image] =>[orig_patent_app_number] => 434836
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/434836 | Apparatus and method for routing signals in a field programmable gate array integrated circuit | May 3, 1995 | Issued |
Array
(
[id] => 3897293
[patent_doc_number] => 05715170
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[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Apparatus for forming input data for a logic simulator'
[patent_app_type] => 1
[patent_app_number] => 8/424624
[patent_app_country] => US
[patent_app_date] => 1995-04-19
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[patent_drawing_sheets_cnt] => 9
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/424624 | Apparatus for forming input data for a logic simulator | Apr 18, 1995 | Issued |
Array
(
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[patent_doc_number] => 05490074
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-06
[patent_title] => 'Constant delay interconnect for coupling configurable logic blocks'
[patent_app_type] => 1
[patent_app_number] => 8/423303
[patent_app_country] => US
[patent_app_date] => 1995-04-18
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[patent_drawing_sheets_cnt] => 52
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[firstpage_image] =>[orig_patent_app_number] => 423303
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/423303 | Constant delay interconnect for coupling configurable logic blocks | Apr 17, 1995 | Issued |
Array
(
[id] => 3840899
[patent_doc_number] => 05712790
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Method of power reduction in pla\'s'
[patent_app_type] => 1
[patent_app_number] => 8/419772
[patent_app_country] => US
[patent_app_date] => 1995-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[firstpage_image] =>[orig_patent_app_number] => 419772
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/419772 | Method of power reduction in pla's | Apr 10, 1995 | Issued |
| 08/414574 | SYSTEM FOR OPTIMIZING POWER NETWORK DESIGN RELIABILITY | Mar 30, 1995 | Abandoned |
Array
(
[id] => 3657585
[patent_doc_number] => 05638305
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[patent_issue_date] => 1997-06-10
[patent_title] => 'Vibration/noise control system'
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[patent_app_number] => 8/410273
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[firstpage_image] =>[orig_patent_app_number] => 410273
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/410273 | Vibration/noise control system | Mar 23, 1995 | Issued |
Array
(
[id] => 3564793
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[patent_issue_date] => 1996-03-19
[patent_title] => 'Apparatus and method for estimating time delays using unmapped combinational logic networks'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 409627
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/409627 | Apparatus and method for estimating time delays using unmapped combinational logic networks | Mar 22, 1995 | Issued |
Array
(
[id] => 3656615
[patent_doc_number] => 05629858
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'CMOS transistor network to gate level model extractor for simulation, verification and test generation'
[patent_app_type] => 1
[patent_app_number] => 8/406283
[patent_app_country] => US
[patent_app_date] => 1995-03-17
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/406283 | CMOS transistor network to gate level model extractor for simulation, verification and test generation | Mar 16, 1995 | Issued |
Array
(
[id] => 3733055
[patent_doc_number] => 05701246
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'Suspension control apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/405873
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[firstpage_image] =>[orig_patent_app_number] => 405873
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/405873 | Suspension control apparatus | Mar 16, 1995 | Issued |
Array
(
[id] => 3706281
[patent_doc_number] => 05677841
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[patent_issue_date] => 1997-10-14
[patent_title] => 'Control target surveillance system'
[patent_app_type] => 1
[patent_app_number] => 8/401270
[patent_app_country] => US
[patent_app_date] => 1995-03-09
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Array
(
[id] => 3756003
[patent_doc_number] => 05801943
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[patent_issue_date] => 1998-09-01
[patent_title] => 'Traffic surveillance and simulation apparatus'
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[firstpage_image] =>[orig_patent_app_number] => 398770
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/398770 | Traffic surveillance and simulation apparatus | Mar 5, 1995 | Issued |
Array
(
[id] => 3891678
[patent_doc_number] => 05748487
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[patent_issue_date] => 1998-05-05
[patent_title] => 'System and method for generating a hazard-free asynchronous circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/381081 | System and method for generating a hazard-free asynchronous circuit | Jan 30, 1995 | Issued |
Array
(
[id] => 3549272
[patent_doc_number] => 05481476
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[patent_title] => 'Apparatus for interactive self-modeling mixture analysis'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/379829 | Apparatus for interactive self-modeling mixture analysis | Jan 26, 1995 | Issued |
Array
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[firstpage_image] =>[orig_patent_app_number] => 377404
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/377404 | Logic simulation method and logic simulator | Jan 23, 1995 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/372316 | System and method for hierarchical device extraction | Jan 12, 1995 | Issued |
Array
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Array
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Array
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