Search

Vincent N. Trans

Examiner (ID: 10207)

Most Active Art Unit
2304
Art Unit(s)
2763, 2304, 2899, OPET, 2787
Total Applications
1054
Issued Applications
820
Pending Applications
21
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3572317 [patent_doc_number] => 05526277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'ECAD system for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic descriptions thereof' [patent_app_type] => 1 [patent_app_number] => 8/355105 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 11735 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526277.pdf [firstpage_image] =>[orig_patent_app_number] => 355105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355105
ECAD system for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic descriptions thereof Dec 12, 1994 Issued
Array ( [id] => 3602375 [patent_doc_number] => 05521836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Method for determining instance placements in circuit layouts' [patent_app_type] => 1 [patent_app_number] => 8/355310 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3414 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521836.pdf [firstpage_image] =>[orig_patent_app_number] => 355310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355310
Method for determining instance placements in circuit layouts Dec 11, 1994 Issued
Array ( [id] => 3669775 [patent_doc_number] => 05648920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method and apparatus for deriving total lateral diffusion in metal oxide semiconductor transistors' [patent_app_type] => 1 [patent_app_number] => 8/343403 [patent_app_country] => US [patent_app_date] => 1994-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648920.pdf [firstpage_image] =>[orig_patent_app_number] => 343403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/343403
Method and apparatus for deriving total lateral diffusion in metal oxide semiconductor transistors Nov 21, 1994 Issued
Array ( [id] => 3738025 [patent_doc_number] => 05671151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Self-timed logic circuit having zero-latency overhead and method for designing same' [patent_app_type] => 1 [patent_app_number] => 8/339473 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4397 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671151.pdf [firstpage_image] =>[orig_patent_app_number] => 339473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339473
Self-timed logic circuit having zero-latency overhead and method for designing same Nov 13, 1994 Issued
Array ( [id] => 3428298 [patent_doc_number] => 05479357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Circuit designing system' [patent_app_type] => 1 [patent_app_number] => 8/332724 [patent_app_country] => US [patent_app_date] => 1994-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5359 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479357.pdf [firstpage_image] =>[orig_patent_app_number] => 332724 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332724
Circuit designing system Oct 31, 1994 Issued
Array ( [id] => 3584938 [patent_doc_number] => 05523956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Electrical interconnect integrity measuring method' [patent_app_type] => 1 [patent_app_number] => 8/323406 [patent_app_country] => US [patent_app_date] => 1994-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2914 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523956.pdf [firstpage_image] =>[orig_patent_app_number] => 323406 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/323406
Electrical interconnect integrity measuring method Oct 13, 1994 Issued
08/312198 SYSTEM FOR AND METHOD OF CONNECTING A HARDWARE MODELING ELEMENT TO A HARDWARE MODELING SYSTEM Sep 25, 1994 Abandoned
Array ( [id] => 3716589 [patent_doc_number] => 05675771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Mechanism for enabling emulation system users to directly invoke a number of host system facilities for executing host procedures either synchronously or asynchronously in a secure manner through automatically created shell mechanisms' [patent_app_type] => 1 [patent_app_number] => 8/311649 [patent_app_country] => US [patent_app_date] => 1994-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8185 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675771.pdf [firstpage_image] =>[orig_patent_app_number] => 311649 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/311649
Mechanism for enabling emulation system users to directly invoke a number of host system facilities for executing host procedures either synchronously or asynchronously in a secure manner through automatically created shell mechanisms Sep 22, 1994 Issued
Array ( [id] => 3673638 [patent_doc_number] => 05598348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Method and apparatus for analyzing the power network of a VLSI circuit' [patent_app_type] => 1 [patent_app_number] => 8/310936 [patent_app_country] => US [patent_app_date] => 1994-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7750 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598348.pdf [firstpage_image] =>[orig_patent_app_number] => 310936 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/310936
Method and apparatus for analyzing the power network of a VLSI circuit Sep 21, 1994 Issued
Array ( [id] => 3498492 [patent_doc_number] => 05471402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Frequency counter' [patent_app_type] => 1 [patent_app_number] => 8/310228 [patent_app_country] => US [patent_app_date] => 1994-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4823 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471402.pdf [firstpage_image] =>[orig_patent_app_number] => 310228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/310228
Frequency counter Sep 20, 1994 Issued
Array ( [id] => 3671958 [patent_doc_number] => 05625565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'System and method for generating a template for functional logic symbols' [patent_app_type] => 1 [patent_app_number] => 8/303393 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4989 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625565.pdf [firstpage_image] =>[orig_patent_app_number] => 303393 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/303393
System and method for generating a template for functional logic symbols Sep 8, 1994 Issued
Array ( [id] => 3617484 [patent_doc_number] => 05590049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method and system for user programmable design verification for printed circuit boards and multichip modules' [patent_app_type] => 1 [patent_app_number] => 8/302329 [patent_app_country] => US [patent_app_date] => 1994-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3763 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590049.pdf [firstpage_image] =>[orig_patent_app_number] => 302329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/302329
Method and system for user programmable design verification for printed circuit boards and multichip modules Sep 6, 1994 Issued
Array ( [id] => 3678062 [patent_doc_number] => 05600569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Method, system, and apparatus for automatically designing logic circuit, and multiplier' [patent_app_type] => 1 [patent_app_number] => 8/300802 [patent_app_country] => US [patent_app_date] => 1994-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 24927 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600569.pdf [firstpage_image] =>[orig_patent_app_number] => 300802 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/300802
Method, system, and apparatus for automatically designing logic circuit, and multiplier Sep 1, 1994 Issued
Array ( [id] => 3564751 [patent_doc_number] => 05500805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-19 [patent_title] => 'Multiple source equalization design utilizing metal interconnects for gate arrays and embedded arrays' [patent_app_type] => 1 [patent_app_number] => 8/300637 [patent_app_country] => US [patent_app_date] => 1994-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7228 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/500/05500805.pdf [firstpage_image] =>[orig_patent_app_number] => 300637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/300637
Multiple source equalization design utilizing metal interconnects for gate arrays and embedded arrays Sep 1, 1994 Issued
Array ( [id] => 3623760 [patent_doc_number] => 05510999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Multiple source equalization design for gate arrays and embedded arrays' [patent_app_type] => 1 [patent_app_number] => 8/300636 [patent_app_country] => US [patent_app_date] => 1994-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7229 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510999.pdf [firstpage_image] =>[orig_patent_app_number] => 300636 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/300636
Multiple source equalization design for gate arrays and embedded arrays Sep 1, 1994 Issued
Array ( [id] => 3455271 [patent_doc_number] => 05420800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Layout method for a semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/300579 [patent_app_country] => US [patent_app_date] => 1994-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3918 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420800.pdf [firstpage_image] =>[orig_patent_app_number] => 300579 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/300579
Layout method for a semiconductor integrated circuit device Sep 1, 1994 Issued
Array ( [id] => 3536723 [patent_doc_number] => 05541842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'System and method for adjusting accumulated crash-discrimination measures based on crash progress' [patent_app_type] => 1 [patent_app_number] => 8/298844 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2678 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541842.pdf [firstpage_image] =>[orig_patent_app_number] => 298844 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/298844
System and method for adjusting accumulated crash-discrimination measures based on crash progress Aug 30, 1994 Issued
90/003556 COMPARISON AND VERIFICATION SYSTEM FOR LOGIC CIRCUITS AND METHOD THEREOF Aug 28, 1994 Issued
08/290602 CAD APPARATUS FOR LSI OR PRINTED CIRCUIT BOARD Aug 14, 1994 Abandoned
Array ( [id] => 3677898 [patent_doc_number] => 05600558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Data exception reporting system' [patent_app_type] => 1 [patent_app_number] => 8/289470 [patent_app_country] => US [patent_app_date] => 1994-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2727 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600558.pdf [firstpage_image] =>[orig_patent_app_number] => 289470 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/289470
Data exception reporting system Aug 11, 1994 Issued
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