| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1996-06-11
[patent_title] => 'ECAD system for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic descriptions thereof'
[patent_app_type] => 1
[patent_app_number] => 8/355105
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Array
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[patent_doc_number] => 05521836
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Method for determining instance placements in circuit layouts'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 355310
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/355310 | Method for determining instance placements in circuit layouts | Dec 11, 1994 | Issued |
Array
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[patent_doc_number] => 05648920
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Method and apparatus for deriving total lateral diffusion in metal oxide semiconductor transistors'
[patent_app_type] => 1
[patent_app_number] => 8/343403
[patent_app_country] => US
[patent_app_date] => 1994-11-22
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[firstpage_image] =>[orig_patent_app_number] => 343403
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/343403 | Method and apparatus for deriving total lateral diffusion in metal oxide semiconductor transistors | Nov 21, 1994 | Issued |
Array
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[id] => 3738025
[patent_doc_number] => 05671151
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Self-timed logic circuit having zero-latency overhead and method for designing same'
[patent_app_type] => 1
[patent_app_number] => 8/339473
[patent_app_country] => US
[patent_app_date] => 1994-11-14
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[firstpage_image] =>[orig_patent_app_number] => 339473
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/339473 | Self-timed logic circuit having zero-latency overhead and method for designing same | Nov 13, 1994 | Issued |
Array
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[id] => 3428298
[patent_doc_number] => 05479357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Circuit designing system'
[patent_app_type] => 1
[patent_app_number] => 8/332724
[patent_app_country] => US
[patent_app_date] => 1994-11-01
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[firstpage_image] =>[orig_patent_app_number] => 332724
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/332724 | Circuit designing system | Oct 31, 1994 | Issued |
Array
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[id] => 3584938
[patent_doc_number] => 05523956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Electrical interconnect integrity measuring method'
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[patent_app_number] => 8/323406
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[firstpage_image] =>[orig_patent_app_number] => 323406
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/323406 | Electrical interconnect integrity measuring method | Oct 13, 1994 | Issued |
| 08/312198 | SYSTEM FOR AND METHOD OF CONNECTING A HARDWARE MODELING ELEMENT TO A HARDWARE MODELING SYSTEM | Sep 25, 1994 | Abandoned |
Array
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[id] => 3716589
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[patent_issue_date] => 1997-10-07
[patent_title] => 'Mechanism for enabling emulation system users to directly invoke a number of host system facilities for executing host procedures either synchronously or asynchronously in a secure manner through automatically created shell mechanisms'
[patent_app_type] => 1
[patent_app_number] => 8/311649
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[pdf_file] => patents/05/675/05675771.pdf
[firstpage_image] =>[orig_patent_app_number] => 311649
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/311649 | Mechanism for enabling emulation system users to directly invoke a number of host system facilities for executing host procedures either synchronously or asynchronously in a secure manner through automatically created shell mechanisms | Sep 22, 1994 | Issued |
Array
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[id] => 3673638
[patent_doc_number] => 05598348
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[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Method and apparatus for analyzing the power network of a VLSI circuit'
[patent_app_type] => 1
[patent_app_number] => 8/310936
[patent_app_country] => US
[patent_app_date] => 1994-09-22
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[pdf_file] => patents/05/598/05598348.pdf
[firstpage_image] =>[orig_patent_app_number] => 310936
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/310936 | Method and apparatus for analyzing the power network of a VLSI circuit | Sep 21, 1994 | Issued |
Array
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[id] => 3498492
[patent_doc_number] => 05471402
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Frequency counter'
[patent_app_type] => 1
[patent_app_number] => 8/310228
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[patent_app_date] => 1994-09-21
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[firstpage_image] =>[orig_patent_app_number] => 310228
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/310228 | Frequency counter | Sep 20, 1994 | Issued |
Array
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[id] => 3671958
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[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'System and method for generating a template for functional logic symbols'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/303393 | System and method for generating a template for functional logic symbols | Sep 8, 1994 | Issued |
Array
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[firstpage_image] =>[orig_patent_app_number] => 302329
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/302329 | Method and system for user programmable design verification for printed circuit boards and multichip modules | Sep 6, 1994 | Issued |
Array
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[patent_issue_date] => 1997-02-04
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Array
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Array
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Array
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Array
(
[id] => 3536723
[patent_doc_number] => 05541842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'System and method for adjusting accumulated crash-discrimination measures based on crash progress'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298844 | System and method for adjusting accumulated crash-discrimination measures based on crash progress | Aug 30, 1994 | Issued |
| 90/003556 | COMPARISON AND VERIFICATION SYSTEM FOR LOGIC CIRCUITS AND METHOD THEREOF | Aug 28, 1994 | Issued |
| 08/290602 | CAD APPARATUS FOR LSI OR PRINTED CIRCUIT BOARD | Aug 14, 1994 | Abandoned |
Array
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