
Vincent P. Canney
Examiner (ID: 14183)
| Most Active Art Unit | 2305 |
| Art Unit(s) | 2413, 2785, 2300, 2303, 2784, 2709, 2313, 2305 |
| Total Applications | 1739 |
| Issued Applications | 1512 |
| Pending Applications | 12 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3924305
[patent_doc_number] => 05938781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Production interface for an integrated circuit test system'
[patent_app_type] => 1
[patent_app_number] => 9/170490
[patent_app_country] => US
[patent_app_date] => 1998-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4159
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/938/05938781.pdf
[firstpage_image] =>[orig_patent_app_number] => 170490
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/170490 | Production interface for an integrated circuit test system | Oct 12, 1998 | Issued |
Array
(
[id] => 4100587
[patent_doc_number] => 06055654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Method and apparatus for reading compressed test data from memory devices'
[patent_app_type] => 1
[patent_app_number] => 9/133919
[patent_app_country] => US
[patent_app_date] => 1998-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4194
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/055/06055654.pdf
[firstpage_image] =>[orig_patent_app_number] => 133919
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/133919 | Method and apparatus for reading compressed test data from memory devices | Aug 12, 1998 | Issued |
| 09/054793 | METHOD AND APPARATUS FOR TEST DATA GENERATION | Apr 2, 1998 | Issued |
| 09/014503 | ECC-COMPARE PATH OF CACHE DIRECTORY LOGIC IMPROVEMENTS | Jan 27, 1998 | Issued |
Array
(
[id] => 4035451
[patent_doc_number] => 05926485
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Semiconductor testing device with rewrite controller'
[patent_app_type] => 1
[patent_app_number] => 8/894105
[patent_app_country] => US
[patent_app_date] => 1998-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2903
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926485.pdf
[firstpage_image] =>[orig_patent_app_number] => 894105
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/894105 | Semiconductor testing device with rewrite controller | Jan 19, 1998 | Issued |
Array
(
[id] => 4011860
[patent_doc_number] => 05923678
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Pattern data generating system'
[patent_app_type] => 1
[patent_app_number] => 8/992216
[patent_app_country] => US
[patent_app_date] => 1997-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2302
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/923/05923678.pdf
[firstpage_image] =>[orig_patent_app_number] => 992216
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/992216 | Pattern data generating system | Dec 16, 1997 | Issued |
Array
(
[id] => 4027986
[patent_doc_number] => 05907561
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-25
[patent_title] => 'Method to improve testing speed of memory'
[patent_app_type] => 1
[patent_app_number] => 8/992077
[patent_app_country] => US
[patent_app_date] => 1997-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 4581
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/907/05907561.pdf
[firstpage_image] =>[orig_patent_app_number] => 992077
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/992077 | Method to improve testing speed of memory | Dec 16, 1997 | Issued |
Array
(
[id] => 4055222
[patent_doc_number] => 05909452
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Method for avoiding contention during boundary scan testing'
[patent_app_type] => 1
[patent_app_number] => 8/991373
[patent_app_country] => US
[patent_app_date] => 1997-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 7628
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909452.pdf
[firstpage_image] =>[orig_patent_app_number] => 991373
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991373 | Method for avoiding contention during boundary scan testing | Dec 15, 1997 | Issued |
Array
(
[id] => 4062277
[patent_doc_number] => 05870412
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Forward error correction system for packet based real time media'
[patent_app_type] => 1
[patent_app_number] => 8/989483
[patent_app_country] => US
[patent_app_date] => 1997-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5478
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/870/05870412.pdf
[firstpage_image] =>[orig_patent_app_number] => 989483
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/989483 | Forward error correction system for packet based real time media | Dec 11, 1997 | Issued |
Array
(
[id] => 4074437
[patent_doc_number] => 05896400
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/989575
[patent_app_country] => US
[patent_app_date] => 1997-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 7159
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/896/05896400.pdf
[firstpage_image] =>[orig_patent_app_number] => 989575
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/989575 | Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell | Dec 11, 1997 | Issued |
Array
(
[id] => 4028327
[patent_doc_number] => 05881078
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Logic circuit having error detection function and processor including the logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/989414
[patent_app_country] => US
[patent_app_date] => 1997-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 6447
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/881/05881078.pdf
[firstpage_image] =>[orig_patent_app_number] => 989414
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/989414 | Logic circuit having error detection function and processor including the logic circuit | Dec 11, 1997 | Issued |
Array
(
[id] => 3771128
[patent_doc_number] => 05852619
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-22
[patent_title] => 'Pattern generator circuit for semiconductor test system'
[patent_app_type] => 1
[patent_app_number] => 8/986469
[patent_app_country] => US
[patent_app_date] => 1997-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3120
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 317
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/852/05852619.pdf
[firstpage_image] =>[orig_patent_app_number] => 986469
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/986469 | Pattern generator circuit for semiconductor test system | Dec 7, 1997 | Issued |
Array
(
[id] => 3949521
[patent_doc_number] => 05872795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Method and apparatus for scan testing of multi-phase logic'
[patent_app_type] => 1
[patent_app_number] => 8/979195
[patent_app_country] => US
[patent_app_date] => 1997-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2041
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/872/05872795.pdf
[firstpage_image] =>[orig_patent_app_number] => 979195
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979195 | Method and apparatus for scan testing of multi-phase logic | Nov 25, 1997 | Issued |
Array
(
[id] => 3890794
[patent_doc_number] => 05825787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'System and method for accessing a test vector memory'
[patent_app_type] => 1
[patent_app_number] => 8/978163
[patent_app_country] => US
[patent_app_date] => 1997-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2445
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825787.pdf
[firstpage_image] =>[orig_patent_app_number] => 978163
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/978163 | System and method for accessing a test vector memory | Nov 24, 1997 | Issued |
Array
(
[id] => 3803733
[patent_doc_number] => 05841787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Memory programming and test circuitry and methods for implementing the same'
[patent_app_type] => 1
[patent_app_number] => 8/975598
[patent_app_country] => US
[patent_app_date] => 1997-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 4993
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841787.pdf
[firstpage_image] =>[orig_patent_app_number] => 975598
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/975598 | Memory programming and test circuitry and methods for implementing the same | Nov 20, 1997 | Issued |
Array
(
[id] => 3771078
[patent_doc_number] => 05852616
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-22
[patent_title] => 'On-chip operating condition recorder'
[patent_app_type] => 1
[patent_app_number] => 8/971357
[patent_app_country] => US
[patent_app_date] => 1997-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2699
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/852/05852616.pdf
[firstpage_image] =>[orig_patent_app_number] => 971357
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/971357 | On-chip operating condition recorder | Nov 16, 1997 | Issued |
Array
(
[id] => 4055198
[patent_doc_number] => 05909450
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Tool to reconfigure pin connections between a dut and a tester'
[patent_app_type] => 1
[patent_app_number] => 8/970696
[patent_app_country] => US
[patent_app_date] => 1997-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2968
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909450.pdf
[firstpage_image] =>[orig_patent_app_number] => 970696
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/970696 | Tool to reconfigure pin connections between a dut and a tester | Nov 13, 1997 | Issued |
Array
(
[id] => 3780758
[patent_doc_number] => 05850406
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Method for detecting and compensating for missing and/or incorrectly inserted cells in the asynchronous transfer method (ATM)'
[patent_app_type] => 1
[patent_app_number] => 8/930093
[patent_app_country] => US
[patent_app_date] => 1997-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2887
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/850/05850406.pdf
[firstpage_image] =>[orig_patent_app_number] => 930093
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/930093 | Method for detecting and compensating for missing and/or incorrectly inserted cells in the asynchronous transfer method (ATM) | Nov 10, 1997 | Issued |
Array
(
[id] => 3972166
[patent_doc_number] => 05901161
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Initialization data redundancy system'
[patent_app_type] => 1
[patent_app_number] => 8/958045
[patent_app_country] => US
[patent_app_date] => 1997-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2870
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/901/05901161.pdf
[firstpage_image] =>[orig_patent_app_number] => 958045
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/958045 | Initialization data redundancy system | Oct 26, 1997 | Issued |
Array
(
[id] => 3963431
[patent_doc_number] => 05956350
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Built in self repair for DRAMs using on-chip temperature sensing and heating'
[patent_app_type] => 1
[patent_app_number] => 8/958775
[patent_app_country] => US
[patent_app_date] => 1997-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4419
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/956/05956350.pdf
[firstpage_image] =>[orig_patent_app_number] => 958775
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/958775 | Built in self repair for DRAMs using on-chip temperature sensing and heating | Oct 26, 1997 | Issued |