Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3713413 [patent_doc_number] => 05646949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Method and apparatus for generating instructions for use in testing a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/658185 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2623 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646949.pdf [firstpage_image] =>[orig_patent_app_number] => 658185 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658185
Method and apparatus for generating instructions for use in testing a microprocessor Jun 3, 1996 Issued
Array ( [id] => 3728717 [patent_doc_number] => 05617428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Scan test circuit and semiconductor integrated circuit device with scan test circuit' [patent_app_type] => 1 [patent_app_number] => 8/650655 [patent_app_country] => US [patent_app_date] => 1996-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8333 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617428.pdf [firstpage_image] =>[orig_patent_app_number] => 650655 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/650655
Scan test circuit and semiconductor integrated circuit device with scan test circuit May 19, 1996 Issued
Array ( [id] => 3868542 [patent_doc_number] => 05706293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method of testing single-order address memory' [patent_app_type] => 1 [patent_app_number] => 8/650936 [patent_app_country] => US [patent_app_date] => 1996-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2179 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706293.pdf [firstpage_image] =>[orig_patent_app_number] => 650936 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/650936
Method of testing single-order address memory May 16, 1996 Issued
Array ( [id] => 3704064 [patent_doc_number] => 05651014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Rate generator circuit for semiconductor test system' [patent_app_type] => 1 [patent_app_number] => 8/650914 [patent_app_country] => US [patent_app_date] => 1996-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 6723 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/651/05651014.pdf [firstpage_image] =>[orig_patent_app_number] => 650914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/650914
Rate generator circuit for semiconductor test system May 16, 1996 Issued
Array ( [id] => 3698346 [patent_doc_number] => 05644578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Failure memory device' [patent_app_type] => 1 [patent_app_number] => 8/648244 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5863 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644578.pdf [firstpage_image] =>[orig_patent_app_number] => 648244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/648244
Failure memory device May 14, 1996 Issued
Array ( [id] => 3898512 [patent_doc_number] => 05715253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'ROM repair circuit' [patent_app_type] => 1 [patent_app_number] => 8/648452 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3834 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715253.pdf [firstpage_image] =>[orig_patent_app_number] => 648452 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/648452
ROM repair circuit May 14, 1996 Issued
Array ( [id] => 3823082 [patent_doc_number] => 05710779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Real time data observation method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/643444 [patent_app_country] => US [patent_app_date] => 1996-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 29 [patent_no_of_words] => 4097 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710779.pdf [firstpage_image] =>[orig_patent_app_number] => 643444 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643444
Real time data observation method and apparatus May 7, 1996 Issued
Array ( [id] => 3739257 [patent_doc_number] => 05671233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Integrated circuit incorporating a test circuit' [patent_app_type] => 1 [patent_app_number] => 8/646564 [patent_app_country] => US [patent_app_date] => 1996-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5701 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671233.pdf [firstpage_image] =>[orig_patent_app_number] => 646564 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/646564
Integrated circuit incorporating a test circuit May 7, 1996 Issued
Array ( [id] => 3637376 [patent_doc_number] => 05621739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Method and apparatus for buffer self-test and characterization' [patent_app_type] => 1 [patent_app_number] => 8/643954 [patent_app_country] => US [patent_app_date] => 1996-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5216 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621739.pdf [firstpage_image] =>[orig_patent_app_number] => 643954 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643954
Method and apparatus for buffer self-test and characterization May 6, 1996 Issued
Array ( [id] => 3901919 [patent_doc_number] => 05778008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Fault diagnosis method of television camera apparatus' [patent_app_type] => 1 [patent_app_number] => 8/646015 [patent_app_country] => US [patent_app_date] => 1996-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7656 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778008.pdf [firstpage_image] =>[orig_patent_app_number] => 646015 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/646015
Fault diagnosis method of television camera apparatus May 6, 1996 Issued
08/643093 SEMICONDUCTOR MEMORY WITH TEST CIRCUIT May 1, 1996 Abandoned
Array ( [id] => 3673006 [patent_doc_number] => 05625631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Pass through mode for multi-chip-module die' [patent_app_type] => 1 [patent_app_number] => 8/638414 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1045 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625631.pdf [firstpage_image] =>[orig_patent_app_number] => 638414 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638414
Pass through mode for multi-chip-module die Apr 25, 1996 Issued
Array ( [id] => 3672991 [patent_doc_number] => 05625630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Increasing testability by clock transformation' [patent_app_type] => 1 [patent_app_number] => 8/637026 [patent_app_country] => US [patent_app_date] => 1996-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6786 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625630.pdf [firstpage_image] =>[orig_patent_app_number] => 637026 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/637026
Increasing testability by clock transformation Apr 23, 1996 Issued
Array ( [id] => 3704424 [patent_doc_number] => 05661729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Semiconductor memory having built-in self-test circuit' [patent_app_type] => 1 [patent_app_number] => 8/636524 [patent_app_country] => US [patent_app_date] => 1996-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6760 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661729.pdf [firstpage_image] =>[orig_patent_app_number] => 636524 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636524
Semiconductor memory having built-in self-test circuit Apr 22, 1996 Issued
Array ( [id] => 3704482 [patent_doc_number] => 05661733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Automatic test insertion' [patent_app_type] => 1 [patent_app_number] => 8/630185 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1910 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661733.pdf [firstpage_image] =>[orig_patent_app_number] => 630185 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630185
Automatic test insertion Apr 9, 1996 Issued
Array ( [id] => 3565647 [patent_doc_number] => 05574850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Circuitry and method for reconfiguring a flash memory' [patent_app_type] => 1 [patent_app_number] => 8/629785 [patent_app_country] => US [patent_app_date] => 1996-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3787 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574850.pdf [firstpage_image] =>[orig_patent_app_number] => 629785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/629785
Circuitry and method for reconfiguring a flash memory Apr 8, 1996 Issued
Array ( [id] => 3841944 [patent_doc_number] => 05712858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Test methodology for exceeding tester pin count for an asic device' [patent_app_type] => 1 [patent_app_number] => 8/627523 [patent_app_country] => US [patent_app_date] => 1996-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4863 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712858.pdf [firstpage_image] =>[orig_patent_app_number] => 627523 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627523
Test methodology for exceeding tester pin count for an asic device Apr 3, 1996 Issued
Array ( [id] => 3799184 [patent_doc_number] => 05822333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Digital memory testing method' [patent_app_type] => 1 [patent_app_number] => 8/624213 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2118 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822333.pdf [firstpage_image] =>[orig_patent_app_number] => 624213 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/624213
Digital memory testing method Mar 28, 1996 Issued
Array ( [id] => 3757838 [patent_doc_number] => 05802069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Implementing mass storage device functions using host processor memory' [patent_app_type] => 1 [patent_app_number] => 8/627939 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2767 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802069.pdf [firstpage_image] =>[orig_patent_app_number] => 627939 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627939
Implementing mass storage device functions using host processor memory Mar 27, 1996 Issued
Array ( [id] => 3906378 [patent_doc_number] => 05835503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method and apparatus for serially programming a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/623423 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 17766 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835503.pdf [firstpage_image] =>[orig_patent_app_number] => 623423 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623423
Method and apparatus for serially programming a programmable logic device Mar 27, 1996 Issued
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