
Vincent P. Canney
Examiner (ID: 2111)
| Most Active Art Unit | 2305 |
| Art Unit(s) | 2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413 |
| Total Applications | 1739 |
| Issued Applications | 1512 |
| Pending Applications | 12 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3713413
[patent_doc_number] => 05646949
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-08
[patent_title] => 'Method and apparatus for generating instructions for use in testing a microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/658185
[patent_app_country] => US
[patent_app_date] => 1996-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2623
[patent_no_of_claims] => 31
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[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/646/05646949.pdf
[firstpage_image] =>[orig_patent_app_number] => 658185
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/658185 | Method and apparatus for generating instructions for use in testing a microprocessor | Jun 3, 1996 | Issued |
Array
(
[id] => 3728717
[patent_doc_number] => 05617428
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-01
[patent_title] => 'Scan test circuit and semiconductor integrated circuit device with scan test circuit'
[patent_app_type] => 1
[patent_app_number] => 8/650655
[patent_app_country] => US
[patent_app_date] => 1996-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/05/617/05617428.pdf
[firstpage_image] =>[orig_patent_app_number] => 650655
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/650655 | Scan test circuit and semiconductor integrated circuit device with scan test circuit | May 19, 1996 | Issued |
Array
(
[id] => 3868542
[patent_doc_number] => 05706293
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Method of testing single-order address memory'
[patent_app_type] => 1
[patent_app_number] => 8/650936
[patent_app_country] => US
[patent_app_date] => 1996-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/706/05706293.pdf
[firstpage_image] =>[orig_patent_app_number] => 650936
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/650936 | Method of testing single-order address memory | May 16, 1996 | Issued |
Array
(
[id] => 3704064
[patent_doc_number] => 05651014
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'Rate generator circuit for semiconductor test system'
[patent_app_type] => 1
[patent_app_number] => 8/650914
[patent_app_country] => US
[patent_app_date] => 1996-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 6723
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[pdf_file] => patents/05/651/05651014.pdf
[firstpage_image] =>[orig_patent_app_number] => 650914
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/650914 | Rate generator circuit for semiconductor test system | May 16, 1996 | Issued |
Array
(
[id] => 3698346
[patent_doc_number] => 05644578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Failure memory device'
[patent_app_type] => 1
[patent_app_number] => 8/648244
[patent_app_country] => US
[patent_app_date] => 1996-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/644/05644578.pdf
[firstpage_image] =>[orig_patent_app_number] => 648244
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/648244 | Failure memory device | May 14, 1996 | Issued |
Array
(
[id] => 3898512
[patent_doc_number] => 05715253
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'ROM repair circuit'
[patent_app_type] => 1
[patent_app_number] => 8/648452
[patent_app_country] => US
[patent_app_date] => 1996-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/715/05715253.pdf
[firstpage_image] =>[orig_patent_app_number] => 648452
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/648452 | ROM repair circuit | May 14, 1996 | Issued |
Array
(
[id] => 3823082
[patent_doc_number] => 05710779
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-20
[patent_title] => 'Real time data observation method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/643444
[patent_app_country] => US
[patent_app_date] => 1996-05-08
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4097
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[pdf_file] => patents/05/710/05710779.pdf
[firstpage_image] =>[orig_patent_app_number] => 643444
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/643444 | Real time data observation method and apparatus | May 7, 1996 | Issued |
Array
(
[id] => 3739257
[patent_doc_number] => 05671233
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Integrated circuit incorporating a test circuit'
[patent_app_type] => 1
[patent_app_number] => 8/646564
[patent_app_country] => US
[patent_app_date] => 1996-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 5701
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/671/05671233.pdf
[firstpage_image] =>[orig_patent_app_number] => 646564
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/646564 | Integrated circuit incorporating a test circuit | May 7, 1996 | Issued |
Array
(
[id] => 3637376
[patent_doc_number] => 05621739
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'Method and apparatus for buffer self-test and characterization'
[patent_app_type] => 1
[patent_app_number] => 8/643954
[patent_app_country] => US
[patent_app_date] => 1996-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/621/05621739.pdf
[firstpage_image] =>[orig_patent_app_number] => 643954
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/643954 | Method and apparatus for buffer self-test and characterization | May 6, 1996 | Issued |
Array
(
[id] => 3901919
[patent_doc_number] => 05778008
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Fault diagnosis method of television camera apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/646015
[patent_app_country] => US
[patent_app_date] => 1996-05-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/778/05778008.pdf
[firstpage_image] =>[orig_patent_app_number] => 646015
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/646015 | Fault diagnosis method of television camera apparatus | May 6, 1996 | Issued |
| 08/643093 | SEMICONDUCTOR MEMORY WITH TEST CIRCUIT | May 1, 1996 | Abandoned |
Array
(
[id] => 3673006
[patent_doc_number] => 05625631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Pass through mode for multi-chip-module die'
[patent_app_type] => 1
[patent_app_number] => 8/638414
[patent_app_country] => US
[patent_app_date] => 1996-04-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/625/05625631.pdf
[firstpage_image] =>[orig_patent_app_number] => 638414
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/638414 | Pass through mode for multi-chip-module die | Apr 25, 1996 | Issued |
Array
(
[id] => 3672991
[patent_doc_number] => 05625630
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Increasing testability by clock transformation'
[patent_app_type] => 1
[patent_app_number] => 8/637026
[patent_app_country] => US
[patent_app_date] => 1996-04-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/625/05625630.pdf
[firstpage_image] =>[orig_patent_app_number] => 637026
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/637026 | Increasing testability by clock transformation | Apr 23, 1996 | Issued |
Array
(
[id] => 3704424
[patent_doc_number] => 05661729
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Semiconductor memory having built-in self-test circuit'
[patent_app_type] => 1
[patent_app_number] => 8/636524
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[pdf_file] => patents/05/661/05661729.pdf
[firstpage_image] =>[orig_patent_app_number] => 636524
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636524 | Semiconductor memory having built-in self-test circuit | Apr 22, 1996 | Issued |
Array
(
[id] => 3704482
[patent_doc_number] => 05661733
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Automatic test insertion'
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[patent_app_date] => 1996-04-10
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[pdf_file] => patents/05/661/05661733.pdf
[firstpage_image] =>[orig_patent_app_number] => 630185
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/630185 | Automatic test insertion | Apr 9, 1996 | Issued |
Array
(
[id] => 3565647
[patent_doc_number] => 05574850
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Circuitry and method for reconfiguring a flash memory'
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[patent_app_number] => 8/629785
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[pdf_file] => patents/05/574/05574850.pdf
[firstpage_image] =>[orig_patent_app_number] => 629785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/629785 | Circuitry and method for reconfiguring a flash memory | Apr 8, 1996 | Issued |
Array
(
[id] => 3841944
[patent_doc_number] => 05712858
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Test methodology for exceeding tester pin count for an asic device'
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[pdf_file] => patents/05/712/05712858.pdf
[firstpage_image] =>[orig_patent_app_number] => 627523
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/627523 | Test methodology for exceeding tester pin count for an asic device | Apr 3, 1996 | Issued |
Array
(
[id] => 3799184
[patent_doc_number] => 05822333
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Digital memory testing method'
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[patent_app_number] => 8/624213
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[pdf_file] => patents/05/822/05822333.pdf
[firstpage_image] =>[orig_patent_app_number] => 624213
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/624213 | Digital memory testing method | Mar 28, 1996 | Issued |
Array
(
[id] => 3757838
[patent_doc_number] => 05802069
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Implementing mass storage device functions using host processor memory'
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[patent_app_number] => 8/627939
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[pdf_file] => patents/05/802/05802069.pdf
[firstpage_image] =>[orig_patent_app_number] => 627939
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/627939 | Implementing mass storage device functions using host processor memory | Mar 27, 1996 | Issued |
Array
(
[id] => 3906378
[patent_doc_number] => 05835503
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[patent_issue_date] => 1998-11-10
[patent_title] => 'Method and apparatus for serially programming a programmable logic device'
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[pdf_file] => patents/05/835/05835503.pdf
[firstpage_image] =>[orig_patent_app_number] => 623423
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/623423 | Method and apparatus for serially programming a programmable logic device | Mar 27, 1996 | Issued |