Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3893651 [patent_doc_number] => 05805604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Apparatus and method for reading and writing data' [patent_app_type] => 1 [patent_app_number] => 8/624768 [patent_app_country] => US [patent_app_date] => 1996-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9432 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 38 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805604.pdf [firstpage_image] =>[orig_patent_app_number] => 624768 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/624768
Apparatus and method for reading and writing data Mar 26, 1996 Issued
Array ( [id] => 3887068 [patent_doc_number] => 05838897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Debugging a processor using data output during idle bus cycles' [patent_app_type] => 1 [patent_app_number] => 8/606774 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 10635 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838897.pdf [firstpage_image] =>[orig_patent_app_number] => 606774 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/606774
Debugging a processor using data output during idle bus cycles Feb 26, 1996 Issued
Array ( [id] => 3706072 [patent_doc_number] => 05619513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Fast, cost-effective method for memory testing' [patent_app_type] => 1 [patent_app_number] => 8/603562 [patent_app_country] => US [patent_app_date] => 1996-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619513.pdf [firstpage_image] =>[orig_patent_app_number] => 603562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/603562
Fast, cost-effective method for memory testing Feb 20, 1996 Issued
Array ( [id] => 3845859 [patent_doc_number] => 05761213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method and apparatus to determine erroneous value in memory cells using data compression' [patent_app_type] => 1 [patent_app_number] => 8/603963 [patent_app_country] => US [patent_app_date] => 1996-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4230 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761213.pdf [firstpage_image] =>[orig_patent_app_number] => 603963 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/603963
Method and apparatus to determine erroneous value in memory cells using data compression Feb 19, 1996 Issued
Array ( [id] => 3848789 [patent_doc_number] => 05761408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method and system for generating a computer program test suite using dynamic symbolic execution' [patent_app_type] => 1 [patent_app_number] => 8/599719 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 7955 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761408.pdf [firstpage_image] =>[orig_patent_app_number] => 599719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/599719
Method and system for generating a computer program test suite using dynamic symbolic execution Feb 11, 1996 Issued
Array ( [id] => 3609730 [patent_doc_number] => 05559811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Method for identifying untestable and redundant faults in sequential logic circuits.' [patent_app_type] => 1 [patent_app_number] => 8/599289 [patent_app_country] => US [patent_app_date] => 1996-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7932 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559811.pdf [firstpage_image] =>[orig_patent_app_number] => 599289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/599289
Method for identifying untestable and redundant faults in sequential logic circuits. Feb 8, 1996 Issued
Array ( [id] => 3859428 [patent_doc_number] => 05719881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Test pattern generating apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/597956 [patent_app_country] => US [patent_app_date] => 1996-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9609 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719881.pdf [firstpage_image] =>[orig_patent_app_number] => 597956 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/597956
Test pattern generating apparatus and method Feb 6, 1996 Issued
08/597015 SELF TEST OF CORE WITH UNPREDICTABLE LATENCY Feb 4, 1996 Abandoned
Array ( [id] => 3707378 [patent_doc_number] => 05596708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Method and apparatus for the protection of write data in a disk array' [patent_app_type] => 1 [patent_app_number] => 8/591366 [patent_app_country] => US [patent_app_date] => 1996-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5192 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596708.pdf [firstpage_image] =>[orig_patent_app_number] => 591366 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/591366
Method and apparatus for the protection of write data in a disk array Jan 24, 1996 Issued
Array ( [id] => 3692139 [patent_doc_number] => 05633879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Method for integrated circuit design and test' [patent_app_type] => 1 [patent_app_number] => 8/591256 [patent_app_country] => US [patent_app_date] => 1996-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 7819 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633879.pdf [firstpage_image] =>[orig_patent_app_number] => 591256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/591256
Method for integrated circuit design and test Jan 18, 1996 Issued
Array ( [id] => 3742104 [patent_doc_number] => 05636228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Scan register with decoupled scan routing' [patent_app_type] => 1 [patent_app_number] => 8/586356 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3203 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636228.pdf [firstpage_image] =>[orig_patent_app_number] => 586356 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/586356
Scan register with decoupled scan routing Jan 15, 1996 Issued
Array ( [id] => 3657852 [patent_doc_number] => 05629947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Method and apparatus for detecting positive and negative runt pulses simultaneously' [patent_app_type] => 1 [patent_app_number] => 8/585057 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 11727 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629947.pdf [firstpage_image] =>[orig_patent_app_number] => 585057 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/585057
Method and apparatus for detecting positive and negative runt pulses simultaneously Jan 10, 1996 Issued
Array ( [id] => 3805408 [patent_doc_number] => 05727000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Signature analysis usage for multiple fault isolation' [patent_app_type] => 1 [patent_app_number] => 8/579278 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2242 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727000.pdf [firstpage_image] =>[orig_patent_app_number] => 579278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/579278
Signature analysis usage for multiple fault isolation Dec 26, 1995 Issued
Array ( [id] => 3784974 [patent_doc_number] => 05774477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method and apparatus for pseudorandom boundary-scan testing' [patent_app_type] => 1 [patent_app_number] => 8/577454 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3795 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774477.pdf [firstpage_image] =>[orig_patent_app_number] => 577454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/577454
Method and apparatus for pseudorandom boundary-scan testing Dec 21, 1995 Issued
Array ( [id] => 3716536 [patent_doc_number] => 05654970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Array with redundant integrated self-testing scan drivers' [patent_app_type] => 1 [patent_app_number] => 8/575784 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7268 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654970.pdf [firstpage_image] =>[orig_patent_app_number] => 575784 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575784
Array with redundant integrated self-testing scan drivers Dec 21, 1995 Issued
Array ( [id] => 3694013 [patent_doc_number] => 05633999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Workstation-implemented data storage re-routing for server fault-tolerance on computer networks' [patent_app_type] => 1 [patent_app_number] => 8/573865 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 10174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633999.pdf [firstpage_image] =>[orig_patent_app_number] => 573865 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/573865
Workstation-implemented data storage re-routing for server fault-tolerance on computer networks Dec 17, 1995 Issued
Array ( [id] => 3744720 [patent_doc_number] => 05694538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Memory rewriting apparatus' [patent_app_type] => 1 [patent_app_number] => 8/569944 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 10476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694538.pdf [firstpage_image] =>[orig_patent_app_number] => 569944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/569944
Memory rewriting apparatus Dec 7, 1995 Issued
Array ( [id] => 3659925 [patent_doc_number] => 05606568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Method and apparatus for performing serial and parallel scan testing on an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/565337 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3190 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606568.pdf [firstpage_image] =>[orig_patent_app_number] => 565337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565337
Method and apparatus for performing serial and parallel scan testing on an integrated circuit Nov 29, 1995 Issued
Array ( [id] => 3563805 [patent_doc_number] => 05572664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'System for generating floating point test vectors' [patent_app_type] => 1 [patent_app_number] => 8/563140 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6269 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572664.pdf [firstpage_image] =>[orig_patent_app_number] => 563140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563140
System for generating floating point test vectors Nov 26, 1995 Issued
Array ( [id] => 3699926 [patent_doc_number] => 05604755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Memory system reset circuit' [patent_app_type] => 1 [patent_app_number] => 8/565627 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2874 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604755.pdf [firstpage_image] =>[orig_patent_app_number] => 565627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565627
Memory system reset circuit Nov 19, 1995 Issued
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