
Vincent P. Canney
Examiner (ID: 2111)
| Most Active Art Unit | 2305 |
| Art Unit(s) | 2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413 |
| Total Applications | 1739 |
| Issued Applications | 1512 |
| Pending Applications | 12 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3699860
[patent_doc_number] => 05604751
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-18
[patent_title] => 'Time linearity measurement using a frequency locked, dual sequencer automatic test system'
[patent_app_type] => 1
[patent_app_number] => 8/555438
[patent_app_country] => US
[patent_app_date] => 1995-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5788
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/604/05604751.pdf
[firstpage_image] =>[orig_patent_app_number] => 555438
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/555438 | Time linearity measurement using a frequency locked, dual sequencer automatic test system | Nov 8, 1995 | Issued |
Array
(
[id] => 3784919
[patent_doc_number] => 05774473
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Scan latch and test method therefore'
[patent_app_type] => 1
[patent_app_number] => 8/558595
[patent_app_country] => US
[patent_app_date] => 1995-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 9016
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774473.pdf
[firstpage_image] =>[orig_patent_app_number] => 558595
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/558595 | Scan latch and test method therefore | Oct 29, 1995 | Issued |
Array
(
[id] => 3545529
[patent_doc_number] => 05557620
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-17
[patent_title] => 'Quiescent current testing of dynamic logic systems'
[patent_app_type] => 1
[patent_app_number] => 8/533415
[patent_app_country] => US
[patent_app_date] => 1995-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7425
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/557/05557620.pdf
[firstpage_image] =>[orig_patent_app_number] => 533415
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/533415 | Quiescent current testing of dynamic logic systems | Sep 24, 1995 | Issued |
Array
(
[id] => 3633620
[patent_doc_number] => 05612966
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'Automatic data transmission rate detection circuit'
[patent_app_type] => 1
[patent_app_number] => 8/529964
[patent_app_country] => US
[patent_app_date] => 1995-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 5852
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/612/05612966.pdf
[firstpage_image] =>[orig_patent_app_number] => 529964
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/529964 | Automatic data transmission rate detection circuit | Sep 18, 1995 | Issued |
Array
(
[id] => 3529542
[patent_doc_number] => 05506960
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/528642
[patent_app_country] => US
[patent_app_date] => 1995-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4418
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/506/05506960.pdf
[firstpage_image] =>[orig_patent_app_number] => 528642
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/528642 | Data processing system | Sep 13, 1995 | Issued |
| 08/527382 | APPARATUS FOR RECORDING OR ERASING IMAGE SIGNALS IN SEQUENCE | Sep 12, 1995 | Abandoned |
| 08/524954 | ROM REPAIR CIRCUIT | Sep 7, 1995 | Abandoned |
Array
(
[id] => 3705397
[patent_doc_number] => 05596584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Single clock scan latch'
[patent_app_type] => 1
[patent_app_number] => 8/519058
[patent_app_country] => US
[patent_app_date] => 1995-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 9915
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/596/05596584.pdf
[firstpage_image] =>[orig_patent_app_number] => 519058
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519058 | Single clock scan latch | Aug 23, 1995 | Issued |
Array
(
[id] => 3633327
[patent_doc_number] => 05602789
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller'
[patent_app_type] => 1
[patent_app_number] => 8/518024
[patent_app_country] => US
[patent_app_date] => 1995-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 42
[patent_no_of_words] => 22044
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/602/05602789.pdf
[firstpage_image] =>[orig_patent_app_number] => 518024
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/518024 | Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller | Aug 21, 1995 | Issued |
Array
(
[id] => 3583401
[patent_doc_number] => 05539753
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Method and apparatus for output deselecting of data during test'
[patent_app_type] => 1
[patent_app_number] => 8/512688
[patent_app_country] => US
[patent_app_date] => 1995-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2587
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/539/05539753.pdf
[firstpage_image] =>[orig_patent_app_number] => 512688
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/512688 | Method and apparatus for output deselecting of data during test | Aug 9, 1995 | Issued |
| 08/512858 | CIRCUITRY AND METHOD FOR RECONFIGURING A FLASH MEMORY | Aug 7, 1995 | Abandoned |
Array
(
[id] => 3854277
[patent_doc_number] => 05708773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'JTAG interface system for communicating with compliant and non-compliant JTAG devices'
[patent_app_type] => 1
[patent_app_number] => 8/504975
[patent_app_country] => US
[patent_app_date] => 1995-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 6516
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/708/05708773.pdf
[firstpage_image] =>[orig_patent_app_number] => 504975
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/504975 | JTAG interface system for communicating with compliant and non-compliant JTAG devices | Jul 19, 1995 | Issued |
Array
(
[id] => 3559024
[patent_doc_number] => 05546405
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Debug apparatus for an automated semiconductor testing system'
[patent_app_type] => 1
[patent_app_number] => 8/502924
[patent_app_country] => US
[patent_app_date] => 1995-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6580
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/546/05546405.pdf
[firstpage_image] =>[orig_patent_app_number] => 502924
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/502924 | Debug apparatus for an automated semiconductor testing system | Jul 16, 1995 | Issued |
Array
(
[id] => 3583383
[patent_doc_number] => 05539752
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Method and system for automated analysis of semiconductor defect data'
[patent_app_type] => 1
[patent_app_number] => 8/496871
[patent_app_country] => US
[patent_app_date] => 1995-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 7707
[patent_no_of_claims] => 38
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/539/05539752.pdf
[firstpage_image] =>[orig_patent_app_number] => 496871
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/496871 | Method and system for automated analysis of semiconductor defect data | Jun 29, 1995 | Issued |
Array
(
[id] => 3698393
[patent_doc_number] => 05644581
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Method and apparatus for converting logic test vectors to memory test patterns'
[patent_app_type] => 1
[patent_app_number] => 8/494464
[patent_app_country] => US
[patent_app_date] => 1995-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3572
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/644/05644581.pdf
[firstpage_image] =>[orig_patent_app_number] => 494464
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/494464 | Method and apparatus for converting logic test vectors to memory test patterns | Jun 25, 1995 | Issued |
Array
(
[id] => 3667490
[patent_doc_number] => 05659550
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Latent defect handling in EEPROM devices'
[patent_app_type] => 1
[patent_app_number] => 8/494090
[patent_app_country] => US
[patent_app_date] => 1995-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 7883
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/659/05659550.pdf
[firstpage_image] =>[orig_patent_app_number] => 494090
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/494090 | Latent defect handling in EEPROM devices | Jun 22, 1995 | Issued |
Array
(
[id] => 3505025
[patent_doc_number] => 05537532
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Restoration in communications networks'
[patent_app_type] => 1
[patent_app_number] => 8/492222
[patent_app_country] => US
[patent_app_date] => 1995-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5922
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/537/05537532.pdf
[firstpage_image] =>[orig_patent_app_number] => 492222
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/492222 | Restoration in communications networks | Jun 18, 1995 | Issued |
Array
(
[id] => 3672375
[patent_doc_number] => 05657330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Single-chip microprocessor with built-in self-testing function'
[patent_app_type] => 1
[patent_app_number] => 8/491557
[patent_app_country] => US
[patent_app_date] => 1995-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 13193
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/657/05657330.pdf
[firstpage_image] =>[orig_patent_app_number] => 491557
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/491557 | Single-chip microprocessor with built-in self-testing function | Jun 14, 1995 | Issued |
Array
(
[id] => 3602449
[patent_doc_number] => 05568495
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Modular audio data processing architecture'
[patent_app_type] => 1
[patent_app_number] => 8/484418
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5312
[patent_no_of_claims] => 6
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/568/05568495.pdf
[firstpage_image] =>[orig_patent_app_number] => 484418
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484418 | Modular audio data processing architecture | Jun 6, 1995 | Issued |
Array
(
[id] => 3567003
[patent_doc_number] => 05544173
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Delay test coverage without additional dummy latches in a scan-based test design'
[patent_app_type] => 1
[patent_app_number] => 8/486112
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3335
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/544/05544173.pdf
[firstpage_image] =>[orig_patent_app_number] => 486112
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/486112 | Delay test coverage without additional dummy latches in a scan-based test design | Jun 6, 1995 | Issued |