
Vincent P. Canney
Examiner (ID: 2111)
| Most Active Art Unit | 2305 |
| Art Unit(s) | 2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413 |
| Total Applications | 1739 |
| Issued Applications | 1512 |
| Pending Applications | 12 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3842387
[patent_doc_number] => 05760985
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Erasing device'
[patent_app_type] => 1
[patent_app_number] => 8/468572
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2647
[patent_no_of_claims] => 5
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[patent_words_short_claim] => 343
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/760/05760985.pdf
[firstpage_image] =>[orig_patent_app_number] => 468572
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/468572 | Erasing device | Jun 5, 1995 | Issued |
Array
(
[id] => 3715805
[patent_doc_number] => 05675725
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Computer backup system operable with open files'
[patent_app_type] => 1
[patent_app_number] => 8/465925
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675725.pdf
[firstpage_image] =>[orig_patent_app_number] => 465925
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/465925 | Computer backup system operable with open files | Jun 5, 1995 | Issued |
Array
(
[id] => 3623789
[patent_doc_number] => 05566194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Method and apparatus to improve read reliability in semiconductor memories'
[patent_app_type] => 1
[patent_app_number] => 8/471139
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 6802
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[pdf_file] => patents/05/566/05566194.pdf
[firstpage_image] =>[orig_patent_app_number] => 471139
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/471139 | Method and apparatus to improve read reliability in semiconductor memories | Jun 5, 1995 | Issued |
Array
(
[id] => 3515475
[patent_doc_number] => 05570245
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-29
[patent_title] => 'Data erasing device erasing designated data'
[patent_app_type] => 1
[patent_app_number] => 8/465943
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3651
[patent_no_of_claims] => 16
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/570/05570245.pdf
[firstpage_image] =>[orig_patent_app_number] => 465943
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/465943 | Data erasing device erasing designated data | Jun 5, 1995 | Issued |
Array
(
[id] => 3704015
[patent_doc_number] => 05651011
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'Method and apparatus for initiating and controlling test modes within an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/456534
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 5060
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[pdf_file] => patents/05/651/05651011.pdf
[firstpage_image] =>[orig_patent_app_number] => 456534
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/456534 | Method and apparatus for initiating and controlling test modes within an integrated circuit | May 31, 1995 | Issued |
Array
(
[id] => 3560870
[patent_doc_number] => 05546534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Method of operating a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/456370
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3788
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[pdf_file] => patents/05/546/05546534.pdf
[firstpage_image] =>[orig_patent_app_number] => 456370
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/456370 | Method of operating a computer system | May 31, 1995 | Issued |
Array
(
[id] => 3598618
[patent_doc_number] => 05497381
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'Bitstream defect analysis method for integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/458020
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 5170
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497381.pdf
[firstpage_image] =>[orig_patent_app_number] => 458020
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/458020 | Bitstream defect analysis method for integrated circuits | May 31, 1995 | Issued |
Array
(
[id] => 3692110
[patent_doc_number] => 05633877
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Programmable built-in self test method and controller for arrays'
[patent_app_type] => 1
[patent_app_number] => 8/450585
[patent_app_country] => US
[patent_app_date] => 1995-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2647
[patent_no_of_claims] => 18
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/633/05633877.pdf
[firstpage_image] =>[orig_patent_app_number] => 450585
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/450585 | Programmable built-in self test method and controller for arrays | May 30, 1995 | Issued |
Array
(
[id] => 3633792
[patent_doc_number] => 05594742
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-14
[patent_title] => 'Bidirectional trellis coding'
[patent_app_type] => 1
[patent_app_number] => 8/453092
[patent_app_country] => US
[patent_app_date] => 1995-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 9083
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/594/05594742.pdf
[firstpage_image] =>[orig_patent_app_number] => 453092
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/453092 | Bidirectional trellis coding | May 29, 1995 | Issued |
Array
(
[id] => 3538145
[patent_doc_number] => 05541935
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Integrated circuit with test signal buses and test control circuits'
[patent_app_type] => 1
[patent_app_number] => 8/450726
[patent_app_country] => US
[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 3418
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541935.pdf
[firstpage_image] =>[orig_patent_app_number] => 450726
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/450726 | Integrated circuit with test signal buses and test control circuits | May 25, 1995 | Issued |
Array
(
[id] => 3563815
[patent_doc_number] => 05574732
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Test pattern generator'
[patent_app_type] => 1
[patent_app_number] => 8/439968
[patent_app_country] => US
[patent_app_date] => 1995-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/574/05574732.pdf
[firstpage_image] =>[orig_patent_app_number] => 439968
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/439968 | Test pattern generator | May 11, 1995 | Issued |
Array
(
[id] => 3517389
[patent_doc_number] => 05570375
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-29
[patent_title] => 'IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing'
[patent_app_type] => 1
[patent_app_number] => 8/438417
[patent_app_country] => US
[patent_app_date] => 1995-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/570/05570375.pdf
[firstpage_image] =>[orig_patent_app_number] => 438417
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/438417 | IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing | May 9, 1995 | Issued |
| 08/435082 | PROCESS CONTROL SYSTEM FOR ACTIVATING STORAGE DEVICE | May 3, 1995 | Abandoned |
Array
(
[id] => 3537236
[patent_doc_number] => 05528603
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Apparatus and method for testing an integrated circuit using a voltage reference potential and a reference integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/431952
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[pdf_file] => patents/05/528/05528603.pdf
[firstpage_image] =>[orig_patent_app_number] => 431952
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/431952 | Apparatus and method for testing an integrated circuit using a voltage reference potential and a reference integrated circuit | Apr 30, 1995 | Issued |
Array
(
[id] => 3597492
[patent_doc_number] => 05553082
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[patent_issue_date] => 1996-09-03
[patent_title] => 'Built-in self-test for logic circuitry at memory array output'
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[patent_app_number] => 8/432310
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[pdf_file] => patents/05/553/05553082.pdf
[firstpage_image] =>[orig_patent_app_number] => 432310
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/432310 | Built-in self-test for logic circuitry at memory array output | Apr 30, 1995 | Issued |
Array
(
[id] => 3601077
[patent_doc_number] => 05586124
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[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'Strongly fail-safe interface based on concurrent checking'
[patent_app_type] => 1
[patent_app_number] => 8/428228
[patent_app_country] => US
[patent_app_date] => 1995-05-01
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[pdf_file] => patents/05/586/05586124.pdf
[firstpage_image] =>[orig_patent_app_number] => 428228
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/428228 | Strongly fail-safe interface based on concurrent checking | Apr 30, 1995 | Issued |
Array
(
[id] => 3528873
[patent_doc_number] => 05530600
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'Signal processing system including adaptive read equalizer with shut off mode for disk drives'
[patent_app_type] => 1
[patent_app_number] => 8/430321
[patent_app_country] => US
[patent_app_date] => 1995-04-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/530/05530600.pdf
[firstpage_image] =>[orig_patent_app_number] => 430321
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/430321 | Signal processing system including adaptive read equalizer with shut off mode for disk drives | Apr 27, 1995 | Issued |
| 08/431156 | LOW OVERHEAD MEMORY DESIGNS FOR IC TERMINALS | Apr 27, 1995 | Abandoned |
Array
(
[id] => 3775977
[patent_doc_number] => 05844916
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Built in access time comparator'
[patent_app_type] => 1
[patent_app_number] => 8/429544
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[pdf_file] => patents/05/844/05844916.pdf
[firstpage_image] =>[orig_patent_app_number] => 429544
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/429544 | Built in access time comparator | Apr 26, 1995 | Issued |
Array
(
[id] => 3605372
[patent_doc_number] => 05522030
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[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Fault control system for communications buses in multi-processor system'
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[pdf_file] => patents/05/522/05522030.pdf
[firstpage_image] =>[orig_patent_app_number] => 418154
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/418154 | Fault control system for communications buses in multi-processor system | Apr 5, 1995 | Issued |