| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3623703
[patent_doc_number] => 05566188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Low cost timing generator for automatic test equipment operating at high data rates'
[patent_app_type] => 1
[patent_app_number] => 8/413063
[patent_app_country] => US
[patent_app_date] => 1995-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7390
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/566/05566188.pdf
[firstpage_image] =>[orig_patent_app_number] => 413063
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/413063 | Low cost timing generator for automatic test equipment operating at high data rates | Mar 28, 1995 | Issued |
| 08/408189 | DATA ERASING DEVICE ERASING DESIGNATED AREA | Mar 21, 1995 | Abandoned |
| 08/408187 | ERASING DEVICE | Mar 21, 1995 | Abandoned |
Array
(
[id] => 3525859
[patent_doc_number] => 05487074
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-23
[patent_title] => 'Boundary scan testing using clocked signal'
[patent_app_type] => 1
[patent_app_number] => 8/406571
[patent_app_country] => US
[patent_app_date] => 1995-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4974
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/487/05487074.pdf
[firstpage_image] =>[orig_patent_app_number] => 406571
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/406571 | Boundary scan testing using clocked signal | Mar 19, 1995 | Issued |
Array
(
[id] => 3499697
[patent_doc_number] => 05471478
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Flash EEPROM array data and header file structure'
[patent_app_type] => 1
[patent_app_number] => 8/401942
[patent_app_country] => US
[patent_app_date] => 1995-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6143
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/471/05471478.pdf
[firstpage_image] =>[orig_patent_app_number] => 401942
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/401942 | Flash EEPROM array data and header file structure | Mar 9, 1995 | Issued |
Array
(
[id] => 3526100
[patent_doc_number] => 05513316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Method and apparatus for exercising an integrated software system'
[patent_app_type] => 1
[patent_app_number] => 8/396275
[patent_app_country] => US
[patent_app_date] => 1995-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 8703
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513316.pdf
[firstpage_image] =>[orig_patent_app_number] => 396275
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/396275 | Method and apparatus for exercising an integrated software system | Feb 27, 1995 | Issued |
Array
(
[id] => 3659879
[patent_doc_number] => 05606565
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Method of applying boundary test patterns'
[patent_app_type] => 1
[patent_app_number] => 8/388655
[patent_app_country] => US
[patent_app_date] => 1995-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3503
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/606/05606565.pdf
[firstpage_image] =>[orig_patent_app_number] => 388655
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/388655 | Method of applying boundary test patterns | Feb 13, 1995 | Issued |
Array
(
[id] => 3573676
[patent_doc_number] => 05526364
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-11
[patent_title] => 'Apparatus for entering and executing test mode operations for memory'
[patent_app_type] => 1
[patent_app_number] => 8/386704
[patent_app_country] => US
[patent_app_date] => 1995-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2404
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/526/05526364.pdf
[firstpage_image] =>[orig_patent_app_number] => 386704
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/386704 | Apparatus for entering and executing test mode operations for memory | Feb 9, 1995 | Issued |
Array
(
[id] => 3667437
[patent_doc_number] => 05659547
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Script-based system for testing a multi-user computer system'
[patent_app_type] => 1
[patent_app_number] => 8/385369
[patent_app_country] => US
[patent_app_date] => 1995-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 15
[patent_no_of_words] => 15545
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/659/05659547.pdf
[firstpage_image] =>[orig_patent_app_number] => 385369
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/385369 | Script-based system for testing a multi-user computer system | Feb 6, 1995 | Issued |
Array
(
[id] => 3563787
[patent_doc_number] => 05574730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Bussed test access port interface and method for testing and controlling system logic boards'
[patent_app_type] => 1
[patent_app_number] => 8/381046
[patent_app_country] => US
[patent_app_date] => 1995-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 8594
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/574/05574730.pdf
[firstpage_image] =>[orig_patent_app_number] => 381046
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/381046 | Bussed test access port interface and method for testing and controlling system logic boards | Jan 30, 1995 | Issued |
| 08/380327 | APPARATUS FOR RECORDING OR ERASING IMAGE SIGNALS IN SEQUENCE | Jan 29, 1995 | Abandoned |
Array
(
[id] => 3564408
[patent_doc_number] => 05519715
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Full-speed microprocessor testing employing boundary scan'
[patent_app_type] => 1
[patent_app_number] => 8/379770
[patent_app_country] => US
[patent_app_date] => 1995-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 9355
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/519/05519715.pdf
[firstpage_image] =>[orig_patent_app_number] => 379770
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/379770 | Full-speed microprocessor testing employing boundary scan | Jan 26, 1995 | Issued |
Array
(
[id] => 3526070
[patent_doc_number] => 05513314
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Fault tolerant NFS server system and mirroring protocol'
[patent_app_type] => 1
[patent_app_number] => 8/378966
[patent_app_country] => US
[patent_app_date] => 1995-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 10030
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513314.pdf
[firstpage_image] =>[orig_patent_app_number] => 378966
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/378966 | Fault tolerant NFS server system and mirroring protocol | Jan 26, 1995 | Issued |
Array
(
[id] => 3598590
[patent_doc_number] => 05497379
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'Method and apparatus for selectable parallel execution of test operations'
[patent_app_type] => 1
[patent_app_number] => 8/378343
[patent_app_country] => US
[patent_app_date] => 1995-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 45
[patent_no_of_words] => 20504
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497379.pdf
[firstpage_image] =>[orig_patent_app_number] => 378343
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/378343 | Method and apparatus for selectable parallel execution of test operations | Jan 25, 1995 | Issued |
Array
(
[id] => 3592979
[patent_doc_number] => 05581563
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Design for testability technique of CMOS and BICMOS ICS'
[patent_app_type] => 1
[patent_app_number] => 8/379317
[patent_app_country] => US
[patent_app_date] => 1995-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 5063
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581563.pdf
[firstpage_image] =>[orig_patent_app_number] => 379317
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/379317 | Design for testability technique of CMOS and BICMOS ICS | Jan 23, 1995 | Issued |
Array
(
[id] => 3537251
[patent_doc_number] => 05528604
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Test pattern generation for an electronic circuit using a transformed circuit description'
[patent_app_type] => 1
[patent_app_number] => 8/374948
[patent_app_country] => US
[patent_app_date] => 1995-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 4013
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528604.pdf
[firstpage_image] =>[orig_patent_app_number] => 374948
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/374948 | Test pattern generation for an electronic circuit using a transformed circuit description | Jan 17, 1995 | Issued |
| 08/366075 | METHOD FOR IDENTIFYING UNTESTABLE & REDUNDANT FAULTS IN SEQUENTIAL LOGIC CIRCUITS | Dec 28, 1994 | Abandoned |
Array
(
[id] => 3538158
[patent_doc_number] => 05541936
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Diagnostic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/365451
[patent_app_country] => US
[patent_app_date] => 1994-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3211
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541936.pdf
[firstpage_image] =>[orig_patent_app_number] => 365451
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/365451 | Diagnostic circuit | Dec 27, 1994 | Issued |
Array
(
[id] => 3527741
[patent_doc_number] => 05577050
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Method and apparatus for configurable build-in self-repairing of ASIC memories design'
[patent_app_type] => 1
[patent_app_number] => 8/365286
[patent_app_country] => US
[patent_app_date] => 1994-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3806
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/577/05577050.pdf
[firstpage_image] =>[orig_patent_app_number] => 365286
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/365286 | Method and apparatus for configurable build-in self-repairing of ASIC memories design | Dec 27, 1994 | Issued |
Array
(
[id] => 3498482
[patent_doc_number] => 05475693
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Error management processes for flash EEPROM memory arrays'
[patent_app_type] => 1
[patent_app_number] => 8/364546
[patent_app_country] => US
[patent_app_date] => 1994-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7527
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/475/05475693.pdf
[firstpage_image] =>[orig_patent_app_number] => 364546
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/364546 | Error management processes for flash EEPROM memory arrays | Dec 26, 1994 | Issued |