Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3626140 [patent_doc_number] => 05511163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Network adaptor connected to a computer for virus signature recognition in all files on a network' [patent_app_type] => 1 [patent_app_number] => 8/325466 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3107 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511163.pdf [firstpage_image] =>[orig_patent_app_number] => 325466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/325466
Network adaptor connected to a computer for virus signature recognition in all files on a network Dec 18, 1994 Issued
08/357476 LOW OVERHEAD INPUT AND OUTPUT BOUNDARY SCAN CELLS Dec 15, 1994 Abandoned
Array ( [id] => 3598604 [patent_doc_number] => 05497380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Control device for the actuation of switchgears' [patent_app_type] => 1 [patent_app_number] => 8/355696 [patent_app_country] => US [patent_app_date] => 1994-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4859 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497380.pdf [firstpage_image] =>[orig_patent_app_number] => 355696 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355696
Control device for the actuation of switchgears Dec 13, 1994 Issued
Array ( [id] => 3593006 [patent_doc_number] => 05581565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Measuring apparatus used for testing connections between at least two subassemblies' [patent_app_type] => 1 [patent_app_number] => 8/349094 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2492 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581565.pdf [firstpage_image] =>[orig_patent_app_number] => 349094 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/349094
Measuring apparatus used for testing connections between at least two subassemblies Nov 30, 1994 Issued
Array ( [id] => 3542170 [patent_doc_number] => 05583875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Automatic parametric self-testing and grading of a hardware system' [patent_app_type] => 1 [patent_app_number] => 8/345883 [patent_app_country] => US [patent_app_date] => 1994-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2552 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583875.pdf [firstpage_image] =>[orig_patent_app_number] => 345883 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/345883
Automatic parametric self-testing and grading of a hardware system Nov 27, 1994 Issued
08/342525 SELF INITIALIZING AND CORRECTING SHARED RESOURCE BOUNDARY SCAN WITH OUTPUT LATCHING Nov 20, 1994 Abandoned
Array ( [id] => 3472614 [patent_doc_number] => 05469444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels' [patent_app_type] => 1 [patent_app_number] => 8/341955 [patent_app_country] => US [patent_app_date] => 1994-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 13327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469444.pdf [firstpage_image] =>[orig_patent_app_number] => 341955 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341955
Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels Nov 15, 1994 Issued
Array ( [id] => 3518433 [patent_doc_number] => 05515505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Semiconductor integrated circuit with boundary scan circuit' [patent_app_type] => 1 [patent_app_number] => 8/334224 [patent_app_country] => US [patent_app_date] => 1994-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2926 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515505.pdf [firstpage_image] =>[orig_patent_app_number] => 334224 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/334224
Semiconductor integrated circuit with boundary scan circuit Nov 3, 1994 Issued
Array ( [id] => 3592960 [patent_doc_number] => 05581562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Integrated circuit device implemented using a plurality of partially defective integrated circuit chips' [patent_app_type] => 1 [patent_app_number] => 8/325946 [patent_app_country] => US [patent_app_date] => 1994-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6367 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581562.pdf [firstpage_image] =>[orig_patent_app_number] => 325946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/325946
Integrated circuit device implemented using a plurality of partially defective integrated circuit chips Oct 18, 1994 Issued
Array ( [id] => 3560155 [patent_doc_number] => 05548597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Failure diagnosis apparatus and a method thereof' [patent_app_type] => 1 [patent_app_number] => 8/322557 [patent_app_country] => US [patent_app_date] => 1994-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3877 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548597.pdf [firstpage_image] =>[orig_patent_app_number] => 322557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/322557
Failure diagnosis apparatus and a method thereof Oct 12, 1994 Issued
Array ( [id] => 3419670 [patent_doc_number] => 05461630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Magnetic recorder/reproducer' [patent_app_type] => 1 [patent_app_number] => 8/316480 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5166 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/461/05461630.pdf [firstpage_image] =>[orig_patent_app_number] => 316480 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/316480
Magnetic recorder/reproducer Oct 2, 1994 Issued
Array ( [id] => 3491195 [patent_doc_number] => 05446598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Signal processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/313408 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5955 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446598.pdf [firstpage_image] =>[orig_patent_app_number] => 313408 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/313408
Signal processing apparatus Sep 26, 1994 Issued
Array ( [id] => 3537208 [patent_doc_number] => 05528601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Scannable latch for multiplexor control' [patent_app_type] => 1 [patent_app_number] => 8/308007 [patent_app_country] => US [patent_app_date] => 1994-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2944 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528601.pdf [firstpage_image] =>[orig_patent_app_number] => 308007 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/308007
Scannable latch for multiplexor control Sep 15, 1994 Issued
Array ( [id] => 3084029 [patent_doc_number] => RE035032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Electronic reminder system' [patent_app_type] => 2 [patent_app_number] => 8/292909 [patent_app_country] => US [patent_app_date] => 1994-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6299 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035032.pdf [firstpage_image] =>[orig_patent_app_number] => 292909 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/292909
Electronic reminder system Aug 18, 1994 Issued
Array ( [id] => 3567700 [patent_doc_number] => 05502731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Delay test coverage without additional dummy latches in a scan-based test design' [patent_app_type] => 1 [patent_app_number] => 8/292375 [patent_app_country] => US [patent_app_date] => 1994-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3335 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502731.pdf [firstpage_image] =>[orig_patent_app_number] => 292375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/292375
Delay test coverage without additional dummy latches in a scan-based test design Aug 17, 1994 Issued
Array ( [id] => 3707345 [patent_doc_number] => 05596706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Highly reliable online system' [patent_app_type] => 1 [patent_app_number] => 8/288584 [patent_app_country] => US [patent_app_date] => 1994-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 39 [patent_no_of_words] => 10338 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596706.pdf [firstpage_image] =>[orig_patent_app_number] => 288584 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/288584
Highly reliable online system Aug 9, 1994 Issued
Array ( [id] => 3135884 [patent_doc_number] => 05436881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Method and apparatus for detecting pulse signal for generating clock from recording medium' [patent_app_type] => 1 [patent_app_number] => 8/288887 [patent_app_country] => US [patent_app_date] => 1994-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3092 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436881.pdf [firstpage_image] =>[orig_patent_app_number] => 288887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/288887
Method and apparatus for detecting pulse signal for generating clock from recording medium Aug 9, 1994 Issued
Array ( [id] => 3433451 [patent_doc_number] => 05459741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Error correction method' [patent_app_type] => 1 [patent_app_number] => 8/284289 [patent_app_country] => US [patent_app_date] => 1994-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4356 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459741.pdf [firstpage_image] =>[orig_patent_app_number] => 284289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/284289
Error correction method Aug 1, 1994 Issued
Array ( [id] => 3430813 [patent_doc_number] => 05435004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Computerized system and method for data backup' [patent_app_type] => 1 [patent_app_number] => 8/278196 [patent_app_country] => US [patent_app_date] => 1994-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/435/05435004.pdf [firstpage_image] =>[orig_patent_app_number] => 278196 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/278196
Computerized system and method for data backup Jul 20, 1994 Issued
Array ( [id] => 3599926 [patent_doc_number] => 05497462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Method and circuit for protecting circuit configurations having an electrically programmable non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/276166 [patent_app_country] => US [patent_app_date] => 1994-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 4462 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497462.pdf [firstpage_image] =>[orig_patent_app_number] => 276166 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/276166
Method and circuit for protecting circuit configurations having an electrically programmable non-volatile memory Jul 14, 1994 Issued
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