| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3432747
[patent_doc_number] => 05479653
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Disk array apparatus and method which supports compound raid configurations and spareless hot sparing'
[patent_app_type] => 1
[patent_app_number] => 8/275176
[patent_app_country] => US
[patent_app_date] => 1994-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4453
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479653.pdf
[firstpage_image] =>[orig_patent_app_number] => 275176
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/275176 | Disk array apparatus and method which supports compound raid configurations and spareless hot sparing | Jul 13, 1994 | Issued |
Array
(
[id] => 3483305
[patent_doc_number] => 05477551
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-19
[patent_title] => 'Apparatus and method for optimal error correcting code to parity conversion'
[patent_app_type] => 1
[patent_app_number] => 8/224398
[patent_app_country] => US
[patent_app_date] => 1994-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3536
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/477/05477551.pdf
[firstpage_image] =>[orig_patent_app_number] => 224398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/224398 | Apparatus and method for optimal error correcting code to parity conversion | Jul 4, 1994 | Issued |
Array
(
[id] => 3633164
[patent_doc_number] => 05615331
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'System and method for debugging a computing system'
[patent_app_type] => 1
[patent_app_number] => 8/265376
[patent_app_country] => US
[patent_app_date] => 1994-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8704
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/615/05615331.pdf
[firstpage_image] =>[orig_patent_app_number] => 265376
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/265376 | System and method for debugging a computing system | Jun 22, 1994 | Issued |
Array
(
[id] => 3502940
[patent_doc_number] => 05440726
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Progressive retry method and apparatus having reusable software modules for software failure recovery in multi-process message-passing applications'
[patent_app_type] => 1
[patent_app_number] => 8/263916
[patent_app_country] => US
[patent_app_date] => 1994-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 17699
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440726.pdf
[firstpage_image] =>[orig_patent_app_number] => 263916
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/263916 | Progressive retry method and apparatus having reusable software modules for software failure recovery in multi-process message-passing applications | Jun 21, 1994 | Issued |
| 08/262426 | FAST, COST-EFFECTIVE METHOD FOR MEMORY TESTING | Jun 19, 1994 | Abandoned |
Array
(
[id] => 3537310
[patent_doc_number] => 05504882
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Fault tolerant data storage subsystem employing hierarchically arranged controllers'
[patent_app_type] => 1
[patent_app_number] => 8/263896
[patent_app_country] => US
[patent_app_date] => 1994-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3223
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/504/05504882.pdf
[firstpage_image] =>[orig_patent_app_number] => 263896
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/263896 | Fault tolerant data storage subsystem employing hierarchically arranged controllers | Jun 19, 1994 | Issued |
Array
(
[id] => 3474224
[patent_doc_number] => 05469554
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Detecting the presence of a device on a computer system bus by altering the bus termination'
[patent_app_type] => 1
[patent_app_number] => 8/259636
[patent_app_country] => US
[patent_app_date] => 1994-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4124
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/469/05469554.pdf
[firstpage_image] =>[orig_patent_app_number] => 259636
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/259636 | Detecting the presence of a device on a computer system bus by altering the bus termination | Jun 13, 1994 | Issued |
Array
(
[id] => 3429105
[patent_doc_number] => 05479413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Method for testing large memory arrays during system initialization'
[patent_app_type] => 1
[patent_app_number] => 8/254816
[patent_app_country] => US
[patent_app_date] => 1994-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2772
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 391
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479413.pdf
[firstpage_image] =>[orig_patent_app_number] => 254816
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/254816 | Method for testing large memory arrays during system initialization | Jun 5, 1994 | Issued |
Array
(
[id] => 3418622
[patent_doc_number] => 05438573
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Flash EEPROM array data and header file structure'
[patent_app_type] => 1
[patent_app_number] => 8/252052
[patent_app_country] => US
[patent_app_date] => 1994-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6141
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/438/05438573.pdf
[firstpage_image] =>[orig_patent_app_number] => 252052
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/252052 | Flash EEPROM array data and header file structure | May 31, 1994 | Issued |
| 08/252026 | SYSTEM FOR GENERATING FLOATING POINT TEST VECTORS | May 31, 1994 | Abandoned |
Array
(
[id] => 3681312
[patent_doc_number] => 05600787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Method and data processing system for verifying circuit test vectors'
[patent_app_type] => 1
[patent_app_number] => 8/251068
[patent_app_country] => US
[patent_app_date] => 1994-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 42
[patent_no_of_words] => 25319
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600787.pdf
[firstpage_image] =>[orig_patent_app_number] => 251068
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/251068 | Method and data processing system for verifying circuit test vectors | May 30, 1994 | Issued |
Array
(
[id] => 3590857
[patent_doc_number] => 05499249
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-12
[patent_title] => 'Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)'
[patent_app_type] => 1
[patent_app_number] => 8/251550
[patent_app_country] => US
[patent_app_date] => 1994-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4808
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/499/05499249.pdf
[firstpage_image] =>[orig_patent_app_number] => 251550
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/251550 | Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs) | May 30, 1994 | Issued |
Array
(
[id] => 3524116
[patent_doc_number] => 05513187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Process for testing integrated circuits with at least one logic circuit and testable integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/193152
[patent_app_country] => US
[patent_app_date] => 1994-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4665
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513187.pdf
[firstpage_image] =>[orig_patent_app_number] => 193152
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/193152 | Process for testing integrated circuits with at least one logic circuit and testable integrated circuit | May 25, 1994 | Issued |
Array
(
[id] => 3605454
[patent_doc_number] => 05522037
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Backup control apparatus and method of data processing system'
[patent_app_type] => 1
[patent_app_number] => 8/248954
[patent_app_country] => US
[patent_app_date] => 1994-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 41
[patent_no_of_words] => 13745
[patent_no_of_claims] => 70
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/522/05522037.pdf
[firstpage_image] =>[orig_patent_app_number] => 248954
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/248954 | Backup control apparatus and method of data processing system | May 24, 1994 | Issued |
Array
(
[id] => 3518364
[patent_doc_number] => 05515500
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'Recording apparatus and method for an arrayed recording apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/243416
[patent_app_country] => US
[patent_app_date] => 1994-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 36
[patent_no_of_words] => 15231
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/515/05515500.pdf
[firstpage_image] =>[orig_patent_app_number] => 243416
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/243416 | Recording apparatus and method for an arrayed recording apparatus | May 15, 1994 | Issued |
Array
(
[id] => 3644631
[patent_doc_number] => 05631910
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Information processing system provided with self-diagnosing circuit and the self-diagnosing method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/243517
[patent_app_country] => US
[patent_app_date] => 1994-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 8832
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/631/05631910.pdf
[firstpage_image] =>[orig_patent_app_number] => 243517
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/243517 | Information processing system provided with self-diagnosing circuit and the self-diagnosing method therefor | May 15, 1994 | Issued |
Array
(
[id] => 3456354
[patent_doc_number] => 05420869
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/241466
[patent_app_country] => US
[patent_app_date] => 1994-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6350
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/420/05420869.pdf
[firstpage_image] =>[orig_patent_app_number] => 241466
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/241466 | Semiconductor integrated circuit device | May 10, 1994 | Issued |
| 08/235270 | FAULT TOLERANT MULTI-DROP COMMUNICATIONS SYSTEM | Apr 28, 1994 | Abandoned |
Array
(
[id] => 3439299
[patent_doc_number] => 05455936
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'Debugger operable with only background monitor'
[patent_app_type] => 1
[patent_app_number] => 8/234566
[patent_app_country] => US
[patent_app_date] => 1994-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3579
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/455/05455936.pdf
[firstpage_image] =>[orig_patent_app_number] => 234566
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/234566 | Debugger operable with only background monitor | Apr 27, 1994 | Issued |
Array
(
[id] => 3453077
[patent_doc_number] => 05467357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'EEPROM apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/230456
[patent_app_country] => US
[patent_app_date] => 1994-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5417
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/467/05467357.pdf
[firstpage_image] =>[orig_patent_app_number] => 230456
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/230456 | EEPROM apparatus | Apr 19, 1994 | Issued |