Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3558996 [patent_doc_number] => 05546403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Bidirectional line switch ring network' [patent_app_type] => 1 [patent_app_number] => 8/195586 [patent_app_country] => US [patent_app_date] => 1994-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3654 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546403.pdf [firstpage_image] =>[orig_patent_app_number] => 195586 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/195586
Bidirectional line switch ring network Feb 13, 1994 Issued
Array ( [id] => 3500565 [patent_doc_number] => 05440569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Flip-flop circuits for testing LSI gate arrays' [patent_app_type] => 1 [patent_app_number] => 8/195606 [patent_app_country] => US [patent_app_date] => 1994-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4208 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440569.pdf [firstpage_image] =>[orig_patent_app_number] => 195606 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/195606
Flip-flop circuits for testing LSI gate arrays Feb 13, 1994 Issued
Array ( [id] => 3138644 [patent_doc_number] => 05437023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Noise-tolerant address transmission system for digital telecommunication network' [patent_app_type] => 1 [patent_app_number] => 8/193946 [patent_app_country] => US [patent_app_date] => 1994-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7797 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/437/05437023.pdf [firstpage_image] =>[orig_patent_app_number] => 193946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/193946
Noise-tolerant address transmission system for digital telecommunication network Feb 8, 1994 Issued
Array ( [id] => 3486400 [patent_doc_number] => 05432796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Line Monitoring for SDH signals' [patent_app_type] => 1 [patent_app_number] => 8/191362 [patent_app_country] => US [patent_app_date] => 1994-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3338 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432796.pdf [firstpage_image] =>[orig_patent_app_number] => 191362 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/191362
Line Monitoring for SDH signals Feb 2, 1994 Issued
Array ( [id] => 3565569 [patent_doc_number] => 05500861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-19 [patent_title] => 'Scanning, circuits, systems and methods' [patent_app_type] => 1 [patent_app_number] => 8/188154 [patent_app_country] => US [patent_app_date] => 1994-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6545 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/500/05500861.pdf [firstpage_image] =>[orig_patent_app_number] => 188154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/188154
Scanning, circuits, systems and methods Jan 26, 1994 Issued
Array ( [id] => 3418637 [patent_doc_number] => 05438574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Program debugging device and process' [patent_app_type] => 1 [patent_app_number] => 8/181954 [patent_app_country] => US [patent_app_date] => 1994-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4265 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438574.pdf [firstpage_image] =>[orig_patent_app_number] => 181954 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/181954
Program debugging device and process Jan 17, 1994 Issued
08/177826 QUIESCENT CURRENT TESTING OF DYNAMIC LOGIC SYSTEMS Jan 4, 1994 Abandoned
Array ( [id] => 3468198 [patent_doc_number] => 05473618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Semiconductor integrated circuit having a built-in test circuit' [patent_app_type] => 1 [patent_app_number] => 8/172744 [patent_app_country] => US [patent_app_date] => 1993-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3563 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473618.pdf [firstpage_image] =>[orig_patent_app_number] => 172744 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/172744
Semiconductor integrated circuit having a built-in test circuit Dec 26, 1993 Issued
Array ( [id] => 3624239 [patent_doc_number] => 05535222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Method and apparatus for controlling a plurality of systems via a boundary-scan port during testing' [patent_app_type] => 1 [patent_app_number] => 8/173732 [patent_app_country] => US [patent_app_date] => 1993-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 42 [patent_no_of_words] => 2898 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535222.pdf [firstpage_image] =>[orig_patent_app_number] => 173732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/173732
Method and apparatus for controlling a plurality of systems via a boundary-scan port during testing Dec 22, 1993 Issued
Array ( [id] => 3518810 [patent_doc_number] => 05515530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Method and apparatus for asynchronous, bi-directional communication between first and second logic elements having a fixed priority arbitrator' [patent_app_type] => 1 [patent_app_number] => 8/172436 [patent_app_country] => US [patent_app_date] => 1993-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5465 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515530.pdf [firstpage_image] =>[orig_patent_app_number] => 172436 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/172436
Method and apparatus for asynchronous, bi-directional communication between first and second logic elements having a fixed priority arbitrator Dec 21, 1993 Issued
08/169758 ERASING DEVICE Dec 19, 1993 Abandoned
Array ( [id] => 3490698 [patent_doc_number] => 05400349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Fault tolerant comparator for disk drive controllers' [patent_app_type] => 1 [patent_app_number] => 8/168856 [patent_app_country] => US [patent_app_date] => 1993-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10443 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/400/05400349.pdf [firstpage_image] =>[orig_patent_app_number] => 168856 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/168856
Fault tolerant comparator for disk drive controllers Dec 15, 1993 Issued
08/165581 DATA ERASING DEVICE ERASING DESIGNATED AREA Dec 12, 1993 Abandoned
Array ( [id] => 3079044 [patent_doc_number] => 05361177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Data recording apparatus having sub-code recording function' [patent_app_type] => 1 [patent_app_number] => 8/163599 [patent_app_country] => US [patent_app_date] => 1993-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8434 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361177.pdf [firstpage_image] =>[orig_patent_app_number] => 163599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/163599
Data recording apparatus having sub-code recording function Dec 7, 1993 Issued
Array ( [id] => 3560211 [patent_doc_number] => 05548601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Apparatus and method for diagnosing failures in control system' [patent_app_type] => 1 [patent_app_number] => 8/160126 [patent_app_country] => US [patent_app_date] => 1993-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548601.pdf [firstpage_image] =>[orig_patent_app_number] => 160126 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/160126
Apparatus and method for diagnosing failures in control system Dec 1, 1993 Issued
Array ( [id] => 3559052 [patent_doc_number] => 05546407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Data transmission circuit for checking of memory device' [patent_app_type] => 1 [patent_app_number] => 8/158514 [patent_app_country] => US [patent_app_date] => 1993-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2003 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546407.pdf [firstpage_image] =>[orig_patent_app_number] => 158514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/158514
Data transmission circuit for checking of memory device Nov 28, 1993 Issued
Array ( [id] => 3433303 [patent_doc_number] => 05459732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Method and apparatus for anti-lock brake single channel wheel speed processing with diagnosis' [patent_app_type] => 1 [patent_app_number] => 8/154776 [patent_app_country] => US [patent_app_date] => 1993-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5384 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459732.pdf [firstpage_image] =>[orig_patent_app_number] => 154776 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/154776
Method and apparatus for anti-lock brake single channel wheel speed processing with diagnosis Nov 18, 1993 Issued
08/154356 DATA PROCESSING SYSTEM Nov 17, 1993 Abandoned
Array ( [id] => 3457199 [patent_doc_number] => 05386327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Recording and reproducing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/154155 [patent_app_country] => US [patent_app_date] => 1993-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4788 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386327.pdf [firstpage_image] =>[orig_patent_app_number] => 154155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/154155
Recording and reproducing apparatus Nov 16, 1993 Issued
08/146296 ROM REPAIR CIRCUIT Nov 3, 1993 Abandoned
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