Vincent P. Canney

Array ( [id] => 3070404 [patent_doc_number] => 05339408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Method and apparatus for reducing checking costs in fault tolerant processors' [patent_app_type] => 1 [patent_app_number] => 7/998715 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 23980 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339408.pdf [firstpage_image] =>[orig_patent_app_number] => 998715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3526087 [patent_doc_number] => 05513315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'System and method for automatic testing of computer software' [patent_app_type] => 1 [patent_app_number] => 7/995746 [patent_app_country] => US [patent_app_date] => 1992-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7440 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513315.pdf [firstpage_image] =>[orig_patent_app_number] => 995746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3422934 [patent_doc_number] => 05444714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Communication and exchange processing system' [patent_app_type] => 1 [patent_app_number] => 7/982896 [patent_app_country] => US [patent_app_date] => 1992-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3534 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444714.pdf [firstpage_image] =>[orig_patent_app_number] => 982896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3065003 [patent_doc_number] => 05345453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Circuit arrangement for sampling a binary signal' [patent_app_type] => 1 [patent_app_number] => 7/980816 [patent_app_country] => US [patent_app_date] => 1992-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4403 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/345/05345453.pdf [firstpage_image] =>[orig_patent_app_number] => 980816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3033216 [patent_doc_number] => 05327435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Method for testing a processor module in a computer system' [patent_app_type] => 1 [patent_app_number] => 7/976095 [patent_app_country] => US [patent_app_date] => 1992-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5281 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327435.pdf [firstpage_image] =>[orig_patent_app_number] => 976095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3106497 [patent_doc_number] => 05293386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Integrated semiconductor memory with parallel test capability and redundancy method' [patent_app_type] => 1 [patent_app_number] => 7/974855 [patent_app_country] => US [patent_app_date] => 1992-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 18080 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293386.pdf [firstpage_image] =>[orig_patent_app_number] => 974855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3471730 [patent_doc_number] => 05392300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Dual mode radio communication unit' [patent_app_type] => 1 [patent_app_number] => 7/973896 [patent_app_country] => US [patent_app_date] => 1992-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392300.pdf [firstpage_image] =>[orig_patent_app_number] => 973896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3426166 [patent_doc_number] => 05394410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Differentially coded and guard pulse position modulation for communication networks' [patent_app_type] => 1 [patent_app_number] => 7/968726 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7048 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394410.pdf [firstpage_image] =>[orig_patent_app_number] => 968726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3464986 [patent_doc_number] => 05452311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Method and apparatus to improve read reliability in semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 7/969756 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6798 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452311.pdf [firstpage_image] =>[orig_patent_app_number] => 969756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3436317 [patent_doc_number] => 05416782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Method and apparatus for improving data failure rate testing for memory arrays' [patent_app_type] => 1 [patent_app_number] => 7/969465 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5780 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416782.pdf [firstpage_image] =>[orig_patent_app_number] => 969465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3131895 [patent_doc_number] => 05384788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Apparatus and method for optimal error correcting code to parity conversion' [patent_app_type] => 1 [patent_app_number] => 7/966235 [patent_app_country] => US [patent_app_date] => 1992-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3578 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384788.pdf [firstpage_image] =>[orig_patent_app_number] => 966235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3454691 [patent_doc_number] => 05388108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Delayed initiation of read-modify-write parity operations in a raid level 5 disk array' [patent_app_type] => 1 [patent_app_number] => 7/966106 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4168 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388108.pdf [firstpage_image] =>[orig_patent_app_number] => 966106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3084706 [patent_doc_number] => 05365505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Information reproducing device' [patent_app_type] => 1 [patent_app_number] => 7/960300 [patent_app_country] => US [patent_app_date] => 1992-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 89 [patent_no_of_words] => 15547 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/365/05365505.pdf [firstpage_image] =>[orig_patent_app_number] => 960300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3467474 [patent_doc_number] => 05402430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Parity inversion test system' [patent_app_type] => 1 [patent_app_number] => 7/955826 [patent_app_country] => US [patent_app_date] => 1992-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4967 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402430.pdf [firstpage_image] =>[orig_patent_app_number] => 955826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3548725 [patent_doc_number] => 05495571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Method and system for performing parametric testing of a functional programming interface' [patent_app_type] => 1 [patent_app_number] => 7/954566 [patent_app_country] => US [patent_app_date] => 1992-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4743 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495571.pdf [firstpage_image] =>[orig_patent_app_number] => 954566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3070385 [patent_doc_number] => 05339407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Recovery of cached data from a malfunctioning CPU' [patent_app_type] => 1 [patent_app_number] => 7/954506 [patent_app_country] => US [patent_app_date] => 1992-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5210 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339407.pdf [firstpage_image] =>[orig_patent_app_number] => 954506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3016786 [patent_doc_number] => 05375232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Method and system for asynchronous pre-staging of backup copies in a data processing storage subsystem' [patent_app_type] => 1 [patent_app_number] => 7/949665 [patent_app_country] => US [patent_app_date] => 1992-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5494 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375232.pdf [firstpage_image] =>[orig_patent_app_number] => 949665 [rel_patent_id] =>[rel_patent_doc_number] =>)