Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3061005 [patent_doc_number] => 05305325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Method and a device for supervising and testing majority voting' [patent_app_type] => 1 [patent_app_number] => 7/719000 [patent_app_country] => US [patent_app_date] => 1991-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2053 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/305/05305325.pdf [firstpage_image] =>[orig_patent_app_number] => 719000 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/719000
Method and a device for supervising and testing majority voting Jun 20, 1991 Issued
Array ( [id] => 2895078 [patent_doc_number] => 05268908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Low data delay triple coverage code apparatus for on-the-fly error correction' [patent_app_type] => 1 [patent_app_number] => 7/717677 [patent_app_country] => US [patent_app_date] => 1991-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6656 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268908.pdf [firstpage_image] =>[orig_patent_app_number] => 717677 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/717677
Low data delay triple coverage code apparatus for on-the-fly error correction Jun 18, 1991 Issued
Array ( [id] => 3100393 [patent_doc_number] => 05278838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Recovery from errors in a redundant array of disk drives' [patent_app_type] => 1 [patent_app_number] => 7/717263 [patent_app_country] => US [patent_app_date] => 1991-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5800 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278838.pdf [firstpage_image] =>[orig_patent_app_number] => 717263 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/717263
Recovery from errors in a redundant array of disk drives Jun 17, 1991 Issued
Array ( [id] => 3100583 [patent_doc_number] => 05278848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Bidirectional communication method' [patent_app_type] => 1 [patent_app_number] => 7/716876 [patent_app_country] => US [patent_app_date] => 1991-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9673 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 470 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278848.pdf [firstpage_image] =>[orig_patent_app_number] => 716876 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/716876
Bidirectional communication method Jun 17, 1991 Issued
07/717349 INFORMATION PROCESSING SYSTEM PROVIDED WITH SELF-DIAGNOSING CIRCUIT AND THE SELF-DIAGNOSING METHOD THEREFOR Jun 17, 1991 Abandoned
Array ( [id] => 3041743 [patent_doc_number] => 05317711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Structure and method for monitoring an internal cache' [patent_app_type] => 1 [patent_app_number] => 7/715526 [patent_app_country] => US [patent_app_date] => 1991-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4164 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/317/05317711.pdf [firstpage_image] =>[orig_patent_app_number] => 715526 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/715526
Structure and method for monitoring an internal cache Jun 13, 1991 Issued
Array ( [id] => 2980112 [patent_doc_number] => 05258984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Method and means for distributed sparing in DASD arrays' [patent_app_type] => 1 [patent_app_number] => 7/714969 [patent_app_country] => US [patent_app_date] => 1991-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6483 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258984.pdf [firstpage_image] =>[orig_patent_app_number] => 714969 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/714969
Method and means for distributed sparing in DASD arrays Jun 12, 1991 Issued
Array ( [id] => 2932615 [patent_doc_number] => 05235602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Synchronous/asynchronous I/O channel check and parity check detector' [patent_app_type] => 1 [patent_app_number] => 7/714127 [patent_app_country] => US [patent_app_date] => 1991-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3982 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235602.pdf [firstpage_image] =>[orig_patent_app_number] => 714127 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/714127
Synchronous/asynchronous I/O channel check and parity check detector Jun 10, 1991 Issued
Array ( [id] => 3598757 [patent_doc_number] => 05550845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Method for dynamic testing of digital logic circuits' [patent_app_type] => 1 [patent_app_number] => 7/712468 [patent_app_country] => US [patent_app_date] => 1991-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1902 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550845.pdf [firstpage_image] =>[orig_patent_app_number] => 712468 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/712468
Method for dynamic testing of digital logic circuits Jun 9, 1991 Issued
Array ( [id] => 3100545 [patent_doc_number] => 05278846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Digital signal decoder' [patent_app_type] => 1 [patent_app_number] => 7/712037 [patent_app_country] => US [patent_app_date] => 1991-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3132 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278846.pdf [firstpage_image] =>[orig_patent_app_number] => 712037 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/712037
Digital signal decoder Jun 6, 1991 Issued
Array ( [id] => 3112426 [patent_doc_number] => 05315600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Error correction system including a plurality of processor elements which are capable of performing several kinds of processing for error correction in parallel' [patent_app_type] => 1 [patent_app_number] => 7/711990 [patent_app_country] => US [patent_app_date] => 1991-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3971 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315600.pdf [firstpage_image] =>[orig_patent_app_number] => 711990 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/711990
Error correction system including a plurality of processor elements which are capable of performing several kinds of processing for error correction in parallel Jun 6, 1991 Issued
Array ( [id] => 2808929 [patent_doc_number] => 05140474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Device for recording a digital information signal on a record carrier' [patent_app_type] => 1 [patent_app_number] => 7/712166 [patent_app_country] => US [patent_app_date] => 1991-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 10320 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140474.pdf [firstpage_image] =>[orig_patent_app_number] => 712166 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/712166
Device for recording a digital information signal on a record carrier Jun 5, 1991 Issued
Array ( [id] => 2943695 [patent_doc_number] => 05233615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'Interrupt driven, separately clocked, fault tolerant processor synchronization' [patent_app_type] => 1 [patent_app_number] => 7/711638 [patent_app_country] => US [patent_app_date] => 1991-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2968 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233615.pdf [firstpage_image] =>[orig_patent_app_number] => 711638 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/711638
Interrupt driven, separately clocked, fault tolerant processor synchronization Jun 5, 1991 Issued
Array ( [id] => 2793697 [patent_doc_number] => 05142421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Device for recording a digital information signal on a record carrier' [patent_app_type] => 1 [patent_app_number] => 7/712167 [patent_app_country] => US [patent_app_date] => 1991-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 34 [patent_no_of_words] => 10609 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142421.pdf [firstpage_image] =>[orig_patent_app_number] => 712167 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/712167
Device for recording a digital information signal on a record carrier Jun 5, 1991 Issued
Array ( [id] => 2909437 [patent_doc_number] => 05245615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Diagnostic system and interface for a personal computer' [patent_app_type] => 1 [patent_app_number] => 7/711003 [patent_app_country] => US [patent_app_date] => 1991-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4760 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/245/05245615.pdf [firstpage_image] =>[orig_patent_app_number] => 711003 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/711003
Diagnostic system and interface for a personal computer Jun 5, 1991 Issued
07/710829 FLIP-FLOP CIRCUITS FOR TESTING LSI GATE ARRAYS Jun 4, 1991 Abandoned
Array ( [id] => 3100529 [patent_doc_number] => 05278845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Teletext decoder with error detection and correction' [patent_app_type] => 1 [patent_app_number] => 7/710267 [patent_app_country] => US [patent_app_date] => 1991-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278845.pdf [firstpage_image] =>[orig_patent_app_number] => 710267 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/710267
Teletext decoder with error detection and correction Jun 3, 1991 Issued
Array ( [id] => 2949002 [patent_doc_number] => 05260946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Self-testing and self-configuration in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/709517 [patent_app_country] => US [patent_app_date] => 1991-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6822 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/260/05260946.pdf [firstpage_image] =>[orig_patent_app_number] => 709517 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/709517
Self-testing and self-configuration in an integrated circuit Jun 2, 1991 Issued
Array ( [id] => 2905445 [patent_doc_number] => 05271023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Uninterruptable fault tolerant data processor' [patent_app_type] => 1 [patent_app_number] => 7/709869 [patent_app_country] => US [patent_app_date] => 1991-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2370 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 630 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/271/05271023.pdf [firstpage_image] =>[orig_patent_app_number] => 709869 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/709869
Uninterruptable fault tolerant data processor Jun 2, 1991 Issued
Array ( [id] => 3061076 [patent_doc_number] => 05305329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Delay data setting circuit and method' [patent_app_type] => 1 [patent_app_number] => 7/713996 [patent_app_country] => US [patent_app_date] => 1991-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4103 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/305/05305329.pdf [firstpage_image] =>[orig_patent_app_number] => 713996 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/713996
Delay data setting circuit and method May 30, 1991 Issued
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