
Vincent P. Canney
Examiner (ID: 2111)
| Most Active Art Unit | 2305 |
| Art Unit(s) | 2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413 |
| Total Applications | 1739 |
| Issued Applications | 1512 |
| Pending Applications | 12 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3826318
[patent_doc_number] => 05812563
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Circuit board testing'
[patent_app_type] => 1
[patent_app_number] => 8/883904
[patent_app_country] => US
[patent_app_date] => 1997-06-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/812/05812563.pdf
[firstpage_image] =>[orig_patent_app_number] => 883904
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/883904 | Circuit board testing | Jun 26, 1997 | Issued |
Array
(
[id] => 4028191
[patent_doc_number] => 05881068
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Decode register with scan functionality'
[patent_app_type] => 1
[patent_app_number] => 8/882664
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[patent_app_date] => 1997-06-25
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Array
(
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[patent_doc_number] => 05896396
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[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Method and apparatus for scan test of SRAM for microprocessors without full scan capability'
[patent_app_type] => 1
[patent_app_number] => 8/880929
[patent_app_country] => US
[patent_app_date] => 1997-06-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880929 | Method and apparatus for scan test of SRAM for microprocessors without full scan capability | Jun 22, 1997 | Issued |
Array
(
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[patent_doc_number] => 05790563
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Self test of core with unpredictable latency'
[patent_app_type] => 1
[patent_app_number] => 8/879673
[patent_app_country] => US
[patent_app_date] => 1997-06-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/879673 | Self test of core with unpredictable latency | Jun 22, 1997 | Issued |
Array
(
[id] => 3949477
[patent_doc_number] => 05872792
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[patent_issue_date] => 1999-02-16
[patent_title] => 'Microcomputer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/878485 | Microcomputer | Jun 17, 1997 | Issued |
Array
(
[id] => 4039784
[patent_doc_number] => 05903576
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[patent_issue_date] => 1999-05-11
[patent_title] => 'Memory test system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/877036 | Memory test system | Jun 16, 1997 | Issued |
Array
(
[id] => 3940733
[patent_doc_number] => 05878050
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[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'Method and apparatus for data compare detection of memory errors on a computers memory subsystem'
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[firstpage_image] =>[orig_patent_app_number] => 873448
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/873448 | Method and apparatus for data compare detection of memory errors on a computers memory subsystem | Jun 11, 1997 | Issued |
Array
(
[id] => 3940779
[patent_doc_number] => 05878053
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[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs'
[patent_app_type] => 1
[patent_app_number] => 8/871086
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[pdf_file] => patents/05/878/05878053.pdf
[firstpage_image] =>[orig_patent_app_number] => 871086
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/871086 | Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs | Jun 8, 1997 | Issued |
Array
(
[id] => 4078749
[patent_doc_number] => 05867504
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[patent_issue_date] => 1999-02-02
[patent_title] => 'Semiconductor memory device with row and column redundancy circuits and a time-shared redundancy circuit test architecture.'
[patent_app_type] => 1
[patent_app_number] => 8/869367
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/869367 | Semiconductor memory device with row and column redundancy circuits and a time-shared redundancy circuit test architecture. | Jun 4, 1997 | Issued |
Array
(
[id] => 4068179
[patent_doc_number] => 05864562
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[patent_issue_date] => 1999-01-26
[patent_title] => 'Circuit for transferring redundancy data of a redundancy circuit inside a memory device by means of a time-shared approach'
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[patent_app_number] => 8/869859
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[firstpage_image] =>[orig_patent_app_number] => 869859
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/869859 | Circuit for transferring redundancy data of a redundancy circuit inside a memory device by means of a time-shared approach | Jun 4, 1997 | Issued |
Array
(
[id] => 4011744
[patent_doc_number] => 05923672
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[patent_issue_date] => 1999-07-13
[patent_title] => 'Multipath antifuse circuit'
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[firstpage_image] =>[orig_patent_app_number] => 870085
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/870085 | Multipath antifuse circuit | Jun 3, 1997 | Issued |
Array
(
[id] => 3784904
[patent_doc_number] => 05774472
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[patent_title] => 'Semiconductor memory device capable of realizing stable test mode operation'
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Array
(
[id] => 4257578
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Array
(
[id] => 3994429
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[patent_title] => 'Test device and its method for testing DSP ICs in the finished product state in a digital video apparatus'
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Array
(
[id] => 3781575
[patent_doc_number] => 05734662
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[patent_title] => 'Period generating device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/849145 | Period generating device | May 28, 1997 | Issued |
Array
(
[id] => 3752908
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Array
(
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Array
(
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Array
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Array
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