Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3826318 [patent_doc_number] => 05812563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Circuit board testing' [patent_app_type] => 1 [patent_app_number] => 8/883904 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4448 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812563.pdf [firstpage_image] =>[orig_patent_app_number] => 883904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883904
Circuit board testing Jun 26, 1997 Issued
Array ( [id] => 4028191 [patent_doc_number] => 05881068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Decode register with scan functionality' [patent_app_type] => 1 [patent_app_number] => 8/882664 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8190 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881068.pdf [firstpage_image] =>[orig_patent_app_number] => 882664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882664
Decode register with scan functionality Jun 24, 1997 Issued
Array ( [id] => 4074382 [patent_doc_number] => 05896396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method and apparatus for scan test of SRAM for microprocessors without full scan capability' [patent_app_type] => 1 [patent_app_number] => 8/880929 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3254 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896396.pdf [firstpage_image] =>[orig_patent_app_number] => 880929 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880929
Method and apparatus for scan test of SRAM for microprocessors without full scan capability Jun 22, 1997 Issued
Array ( [id] => 3832240 [patent_doc_number] => 05790563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Self test of core with unpredictable latency' [patent_app_type] => 1 [patent_app_number] => 8/879673 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3115 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790563.pdf [firstpage_image] =>[orig_patent_app_number] => 879673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879673
Self test of core with unpredictable latency Jun 22, 1997 Issued
Array ( [id] => 3949477 [patent_doc_number] => 05872792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Microcomputer' [patent_app_type] => 1 [patent_app_number] => 8/878485 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3751 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872792.pdf [firstpage_image] =>[orig_patent_app_number] => 878485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878485
Microcomputer Jun 17, 1997 Issued
Array ( [id] => 4039784 [patent_doc_number] => 05903576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Memory test system' [patent_app_type] => 1 [patent_app_number] => 8/877036 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 3945 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903576.pdf [firstpage_image] =>[orig_patent_app_number] => 877036 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877036
Memory test system Jun 16, 1997 Issued
Array ( [id] => 3940733 [patent_doc_number] => 05878050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method and apparatus for data compare detection of memory errors on a computers memory subsystem' [patent_app_type] => 1 [patent_app_number] => 8/873448 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878050.pdf [firstpage_image] =>[orig_patent_app_number] => 873448 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873448
Method and apparatus for data compare detection of memory errors on a computers memory subsystem Jun 11, 1997 Issued
Array ( [id] => 3940779 [patent_doc_number] => 05878053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs' [patent_app_type] => 1 [patent_app_number] => 8/871086 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4069 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878053.pdf [firstpage_image] =>[orig_patent_app_number] => 871086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871086
Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs Jun 8, 1997 Issued
Array ( [id] => 4078749 [patent_doc_number] => 05867504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Semiconductor memory device with row and column redundancy circuits and a time-shared redundancy circuit test architecture.' [patent_app_type] => 1 [patent_app_number] => 8/869367 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8978 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867504.pdf [firstpage_image] =>[orig_patent_app_number] => 869367 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869367
Semiconductor memory device with row and column redundancy circuits and a time-shared redundancy circuit test architecture. Jun 4, 1997 Issued
Array ( [id] => 4068179 [patent_doc_number] => 05864562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Circuit for transferring redundancy data of a redundancy circuit inside a memory device by means of a time-shared approach' [patent_app_type] => 1 [patent_app_number] => 8/869859 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5387 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864562.pdf [firstpage_image] =>[orig_patent_app_number] => 869859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869859
Circuit for transferring redundancy data of a redundancy circuit inside a memory device by means of a time-shared approach Jun 4, 1997 Issued
Array ( [id] => 4011744 [patent_doc_number] => 05923672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Multipath antifuse circuit' [patent_app_type] => 1 [patent_app_number] => 8/870085 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4068 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923672.pdf [firstpage_image] =>[orig_patent_app_number] => 870085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870085
Multipath antifuse circuit Jun 3, 1997 Issued
Array ( [id] => 3784904 [patent_doc_number] => 05774472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Semiconductor memory device capable of realizing stable test mode operation' [patent_app_type] => 1 [patent_app_number] => 8/866369 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8608 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774472.pdf [firstpage_image] =>[orig_patent_app_number] => 866369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866369
Semiconductor memory device capable of realizing stable test mode operation May 29, 1997 Issued
Array ( [id] => 4257578 [patent_doc_number] => 06081911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method and circuit architecture for testing a non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 8/865642 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 19 [patent_no_of_words] => 8736 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081911.pdf [firstpage_image] =>[orig_patent_app_number] => 865642 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865642
Method and circuit architecture for testing a non-volatile memory device May 29, 1997 Issued
Array ( [id] => 3994429 [patent_doc_number] => 05910957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Test device and its method for testing DSP ICs in the finished product state in a digital video apparatus' [patent_app_type] => 1 [patent_app_number] => 8/866316 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3193 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910957.pdf [firstpage_image] =>[orig_patent_app_number] => 866316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866316
Test device and its method for testing DSP ICs in the finished product state in a digital video apparatus May 29, 1997 Issued
Array ( [id] => 3781575 [patent_doc_number] => 05734662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Period generating device' [patent_app_type] => 1 [patent_app_number] => 8/849145 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4246 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734662.pdf [firstpage_image] =>[orig_patent_app_number] => 849145 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/849145
Period generating device May 28, 1997 Issued
Array ( [id] => 3752908 [patent_doc_number] => 05787092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Test chip circuit for on-chip timing characterization' [patent_app_type] => 1 [patent_app_number] => 8/863833 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4432 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787092.pdf [firstpage_image] =>[orig_patent_app_number] => 863833 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863833
Test chip circuit for on-chip timing characterization May 26, 1997 Issued
Array ( [id] => 4035522 [patent_doc_number] => 05926490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Sampled amplitude read channel employing a remod/demod sequence detector guided by an error syndrome' [patent_app_type] => 1 [patent_app_number] => 8/862493 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 9310 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926490.pdf [firstpage_image] =>[orig_patent_app_number] => 862493 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862493
Sampled amplitude read channel employing a remod/demod sequence detector guided by an error syndrome May 22, 1997 Issued
Array ( [id] => 3868334 [patent_doc_number] => 05768289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Dynamically controlling the number of boundary-scan cells in a boundary-scan path' [patent_app_type] => 1 [patent_app_number] => 8/862006 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768289.pdf [firstpage_image] =>[orig_patent_app_number] => 862006 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862006
Dynamically controlling the number of boundary-scan cells in a boundary-scan path May 21, 1997 Issued
Array ( [id] => 3816491 [patent_doc_number] => 05854796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Method of and apparatus for testing semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/861344 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3312 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854796.pdf [firstpage_image] =>[orig_patent_app_number] => 861344 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861344
Method of and apparatus for testing semiconductor memory May 20, 1997 Issued
Array ( [id] => 3868500 [patent_doc_number] => 05768301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Apparatus and method for detecting and correcting pair swap, and implementing a link integrity function in a packet-based data communications system' [patent_app_type] => 1 [patent_app_number] => 8/859017 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 20150 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768301.pdf [firstpage_image] =>[orig_patent_app_number] => 859017 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859017
Apparatus and method for detecting and correcting pair swap, and implementing a link integrity function in a packet-based data communications system May 19, 1997 Issued
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