Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4046171 [patent_doc_number] => 05856981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Reliable connection oriented networks' [patent_app_type] => 1 [patent_app_number] => 8/856895 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7302 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856981.pdf [firstpage_image] =>[orig_patent_app_number] => 856895 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/856895
Reliable connection oriented networks May 14, 1997 Issued
Array ( [id] => 3808837 [patent_doc_number] => 05781558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Diagnostic memory access' [patent_app_type] => 1 [patent_app_number] => 8/854976 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2582 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781558.pdf [firstpage_image] =>[orig_patent_app_number] => 854976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854976
Diagnostic memory access May 12, 1997 Issued
Array ( [id] => 3914256 [patent_doc_number] => 05751729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method and apparatus for efficient self testing of on-chip memory' [patent_app_type] => 1 [patent_app_number] => 8/853314 [patent_app_country] => US [patent_app_date] => 1997-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4245 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751729.pdf [firstpage_image] =>[orig_patent_app_number] => 853314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853314
Method and apparatus for efficient self testing of on-chip memory May 7, 1997 Issued
Array ( [id] => 3775948 [patent_doc_number] => 05844914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Test circuit and method for refresh and descrambling in an integrated memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/850807 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844914.pdf [firstpage_image] =>[orig_patent_app_number] => 850807 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850807
Test circuit and method for refresh and descrambling in an integrated memory circuit May 1, 1997 Issued
Array ( [id] => 4038099 [patent_doc_number] => 05883907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Asymmetrical digital subscriber line (ADSL) block encoder circuit and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/848902 [patent_app_country] => US [patent_app_date] => 1997-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6554 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883907.pdf [firstpage_image] =>[orig_patent_app_number] => 848902 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848902
Asymmetrical digital subscriber line (ADSL) block encoder circuit and method of operation Apr 30, 1997 Issued
Array ( [id] => 3841187 [patent_doc_number] => 05784553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method and system for generating a computer program test suite using dynamic symbolic execution of JAVA programs' [patent_app_type] => 1 [patent_app_number] => 8/846639 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 14430 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784553.pdf [firstpage_image] =>[orig_patent_app_number] => 846639 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846639
Method and system for generating a computer program test suite using dynamic symbolic execution of JAVA programs Apr 29, 1997 Issued
Array ( [id] => 3883982 [patent_doc_number] => 05838694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Dual source data distribution system for integrated circuit tester' [patent_app_type] => 1 [patent_app_number] => 8/847924 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11457 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838694.pdf [firstpage_image] =>[orig_patent_app_number] => 847924 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847924
Dual source data distribution system for integrated circuit tester Apr 27, 1997 Issued
Array ( [id] => 3874597 [patent_doc_number] => 05796749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Delay correction circuit for semiconductor tester' [patent_app_type] => 1 [patent_app_number] => 8/776835 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2583 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796749.pdf [firstpage_image] =>[orig_patent_app_number] => 776835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/776835
Delay correction circuit for semiconductor tester Apr 24, 1997 Issued
Array ( [id] => 3940719 [patent_doc_number] => 05878049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Circuits and methods for read-enabling memory devices synchronously with the reaching of the minimum functionality conditions of the memory cells and reading circuits, particularly for non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 8/840056 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7068 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878049.pdf [firstpage_image] =>[orig_patent_app_number] => 840056 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840056
Circuits and methods for read-enabling memory devices synchronously with the reaching of the minimum functionality conditions of the memory cells and reading circuits, particularly for non-volatile memories Apr 23, 1997 Issued
Array ( [id] => 3940706 [patent_doc_number] => 05878048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Mask ROM having redundancy function' [patent_app_type] => 1 [patent_app_number] => 8/838039 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2965 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878048.pdf [firstpage_image] =>[orig_patent_app_number] => 838039 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838039
Mask ROM having redundancy function Apr 21, 1997 Issued
Array ( [id] => 3994828 [patent_doc_number] => 05862147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Semiconductor device on semiconductor wafer having simple wirings for test and capable of being tested in a short time' [patent_app_type] => 1 [patent_app_number] => 8/845236 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862147.pdf [firstpage_image] =>[orig_patent_app_number] => 845236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/845236
Semiconductor device on semiconductor wafer having simple wirings for test and capable of being tested in a short time Apr 20, 1997 Issued
Array ( [id] => 3906397 [patent_doc_number] => 05835504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Soft fuses using bist for cache self test' [patent_app_type] => 1 [patent_app_number] => 8/839276 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2111 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835504.pdf [firstpage_image] =>[orig_patent_app_number] => 839276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839276
Soft fuses using bist for cache self test Apr 16, 1997 Issued
Array ( [id] => 3972036 [patent_doc_number] => 05901152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Three-value data storing semiconductor memory system' [patent_app_type] => 1 [patent_app_number] => 8/839787 [patent_app_country] => US [patent_app_date] => 1997-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901152.pdf [firstpage_image] =>[orig_patent_app_number] => 839787 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839787
Three-value data storing semiconductor memory system Apr 15, 1997 Issued
Array ( [id] => 3875358 [patent_doc_number] => 05793778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method and apparatus for testing analog and digital circuitry within a larger circuit' [patent_app_type] => 1 [patent_app_number] => 8/832704 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5141 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793778.pdf [firstpage_image] =>[orig_patent_app_number] => 832704 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/832704
Method and apparatus for testing analog and digital circuitry within a larger circuit Apr 10, 1997 Issued
Array ( [id] => 3923766 [patent_doc_number] => 05928374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Scanning device and method for hierarchically forming a scan path for a network' [patent_app_type] => 1 [patent_app_number] => 8/837914 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 69 [patent_no_of_words] => 15573 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928374.pdf [firstpage_image] =>[orig_patent_app_number] => 837914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837914
Scanning device and method for hierarchically forming a scan path for a network Apr 10, 1997 Issued
Array ( [id] => 3987412 [patent_doc_number] => 05905740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Apparatus and method for error correction' [patent_app_type] => 1 [patent_app_number] => 8/841942 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905740.pdf [firstpage_image] =>[orig_patent_app_number] => 841942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841942
Apparatus and method for error correction Apr 7, 1997 Issued
Array ( [id] => 3868347 [patent_doc_number] => 05768290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Semiconductor integrated circuit device incorporating fuse-programmable pass/fail identification circuit and pass/fail determination method thereof' [patent_app_type] => 1 [patent_app_number] => 8/831034 [patent_app_country] => US [patent_app_date] => 1997-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 11752 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768290.pdf [firstpage_image] =>[orig_patent_app_number] => 831034 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/831034
Semiconductor integrated circuit device incorporating fuse-programmable pass/fail identification circuit and pass/fail determination method thereof Mar 31, 1997 Issued
Array ( [id] => 4055530 [patent_doc_number] => 05875195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method and apparatus for error injection techniques' [patent_app_type] => 1 [patent_app_number] => 8/829087 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2309 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875195.pdf [firstpage_image] =>[orig_patent_app_number] => 829087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829087
Method and apparatus for error injection techniques Mar 30, 1997 Issued
Array ( [id] => 3832186 [patent_doc_number] => 05790559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Semiconductor memory testing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/825356 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 11237 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790559.pdf [firstpage_image] =>[orig_patent_app_number] => 825356 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/825356
Semiconductor memory testing apparatus Mar 27, 1997 Issued
Array ( [id] => 3791709 [patent_doc_number] => 05757809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/827038 [patent_app_country] => US [patent_app_date] => 1997-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5238 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757809.pdf [firstpage_image] =>[orig_patent_app_number] => 827038 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827038
Semiconductor memory device Mar 24, 1997 Issued
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