Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3914228 [patent_doc_number] => 05751727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Dynamic latch circuit for utilization with high-speed memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/821155 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5034 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751727.pdf [firstpage_image] =>[orig_patent_app_number] => 821155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821155
Dynamic latch circuit for utilization with high-speed memory arrays Mar 19, 1997 Issued
Array ( [id] => 3822512 [patent_doc_number] => 05831993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Method and apparatus for scan chain with reduced delay penalty' [patent_app_type] => 1 [patent_app_number] => 8/819856 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4338 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831993.pdf [firstpage_image] =>[orig_patent_app_number] => 819856 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/819856
Method and apparatus for scan chain with reduced delay penalty Mar 16, 1997 Issued
Array ( [id] => 3893680 [patent_doc_number] => 05805606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Cache module fault isolation techniques' [patent_app_type] => 1 [patent_app_number] => 8/816627 [patent_app_country] => US [patent_app_date] => 1997-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1741 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805606.pdf [firstpage_image] =>[orig_patent_app_number] => 816627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816627
Cache module fault isolation techniques Mar 12, 1997 Issued
Array ( [id] => 4028230 [patent_doc_number] => 05881071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Digital write-and-read method and signal processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/812286 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 9032 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881071.pdf [firstpage_image] =>[orig_patent_app_number] => 812286 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812286
Digital write-and-read method and signal processing apparatus Mar 5, 1997 Issued
Array ( [id] => 3914386 [patent_doc_number] => 05751737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Boundary scan testing device' [patent_app_type] => 1 [patent_app_number] => 8/805553 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11101 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751737.pdf [firstpage_image] =>[orig_patent_app_number] => 805553 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805553
Boundary scan testing device Feb 25, 1997 Issued
Array ( [id] => 3660082 [patent_doc_number] => 05684809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Semiconductor memory with test circuit' [patent_app_type] => 1 [patent_app_number] => 8/798848 [patent_app_country] => US [patent_app_date] => 1997-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5746 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684809.pdf [firstpage_image] =>[orig_patent_app_number] => 798848 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/798848
Semiconductor memory with test circuit Feb 11, 1997 Issued
Array ( [id] => 3754723 [patent_doc_number] => 05754568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Position measuring system' [patent_app_type] => 1 [patent_app_number] => 8/795230 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2487 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754568.pdf [firstpage_image] =>[orig_patent_app_number] => 795230 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/795230
Position measuring system Feb 9, 1997 Issued
Array ( [id] => 3845902 [patent_doc_number] => 05761216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Bit error measurement system' [patent_app_type] => 1 [patent_app_number] => 8/732303 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 10721 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761216.pdf [firstpage_image] =>[orig_patent_app_number] => 732303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/732303
Bit error measurement system Feb 9, 1997 Issued
Array ( [id] => 3970672 [patent_doc_number] => 05958078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Storage unit and storage unit subsystem' [patent_app_type] => 1 [patent_app_number] => 8/797606 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 42 [patent_no_of_words] => 12136 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958078.pdf [firstpage_image] =>[orig_patent_app_number] => 797606 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797606
Storage unit and storage unit subsystem Feb 6, 1997 Issued
Array ( [id] => 3891108 [patent_doc_number] => 05729552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Process control system for activating storage device' [patent_app_type] => 1 [patent_app_number] => 8/796954 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5812 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729552.pdf [firstpage_image] =>[orig_patent_app_number] => 796954 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/796954
Process control system for activating storage device Feb 6, 1997 Issued
Array ( [id] => 3826821 [patent_doc_number] => 05771243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Method of identifying redundant test patterns' [patent_app_type] => 1 [patent_app_number] => 8/796353 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4375 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771243.pdf [firstpage_image] =>[orig_patent_app_number] => 796353 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/796353
Method of identifying redundant test patterns Feb 6, 1997 Issued
Array ( [id] => 3784959 [patent_doc_number] => 05774476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/794743 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11133 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774476.pdf [firstpage_image] =>[orig_patent_app_number] => 794743 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794743
Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit Feb 2, 1997 Issued
Array ( [id] => 3791870 [patent_doc_number] => 05757820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Method for testing interconnections between integrated circuits using a dynamically generated interconnect topology model' [patent_app_type] => 1 [patent_app_number] => 8/785713 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6131 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757820.pdf [firstpage_image] =>[orig_patent_app_number] => 785713 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785713
Method for testing interconnections between integrated circuits using a dynamically generated interconnect topology model Jan 16, 1997 Issued
Array ( [id] => 3757908 [patent_doc_number] => 05802075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Distributed test pattern generation' [patent_app_type] => 1 [patent_app_number] => 8/783344 [patent_app_country] => US [patent_app_date] => 1997-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13451 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802075.pdf [firstpage_image] =>[orig_patent_app_number] => 783344 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783344
Distributed test pattern generation Jan 15, 1997 Issued
Array ( [id] => 3837087 [patent_doc_number] => 05732091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Self initializing and correcting shared resource boundary scan with output latching' [patent_app_type] => 1 [patent_app_number] => 8/783185 [patent_app_country] => US [patent_app_date] => 1997-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 6441 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732091.pdf [firstpage_image] =>[orig_patent_app_number] => 783185 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783185
Self initializing and correcting shared resource boundary scan with output latching Jan 14, 1997 Issued
Array ( [id] => 3832269 [patent_doc_number] => 05790565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'CMOS integrated circuit failure diagnosis apparatus and diagnostic method' [patent_app_type] => 1 [patent_app_number] => 8/782933 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 41 [patent_no_of_words] => 20677 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790565.pdf [firstpage_image] =>[orig_patent_app_number] => 782933 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/782933
CMOS integrated circuit failure diagnosis apparatus and diagnostic method Jan 12, 1997 Issued
Array ( [id] => 3963416 [patent_doc_number] => 05956349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Semiconductor memory device for high speed data communication capable of accurate testing of pass/fail and memory system employing the same' [patent_app_type] => 1 [patent_app_number] => 8/781248 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6728 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956349.pdf [firstpage_image] =>[orig_patent_app_number] => 781248 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781248
Semiconductor memory device for high speed data communication capable of accurate testing of pass/fail and memory system employing the same Jan 9, 1997 Issued
Array ( [id] => 4087117 [patent_doc_number] => 05966388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'High-speed test system for a memory device' [patent_app_type] => 1 [patent_app_number] => 8/779036 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7971 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966388.pdf [firstpage_image] =>[orig_patent_app_number] => 779036 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779036
High-speed test system for a memory device Jan 5, 1997 Issued
Array ( [id] => 3981647 [patent_doc_number] => 05887002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Preprogramming testing in a field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/778793 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 18007 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887002.pdf [firstpage_image] =>[orig_patent_app_number] => 778793 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778793
Preprogramming testing in a field programmable gate array Jan 2, 1997 Issued
Array ( [id] => 3791738 [patent_doc_number] => 05757811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'System for testing a fault detecting means' [patent_app_type] => 1 [patent_app_number] => 8/779256 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4755 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757811.pdf [firstpage_image] =>[orig_patent_app_number] => 779256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779256
System for testing a fault detecting means Jan 2, 1997 Issued
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