
Vincent P. Canney
Examiner (ID: 2111)
| Most Active Art Unit | 2305 |
| Art Unit(s) | 2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413 |
| Total Applications | 1739 |
| Issued Applications | 1512 |
| Pending Applications | 12 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3914228
[patent_doc_number] => 05751727
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Dynamic latch circuit for utilization with high-speed memory arrays'
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[patent_app_number] => 8/821155
[patent_app_country] => US
[patent_app_date] => 1997-03-20
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[pdf_file] => patents/05/751/05751727.pdf
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Array
(
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[patent_issue_date] => 1998-11-03
[patent_title] => 'Method and apparatus for scan chain with reduced delay penalty'
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Array
(
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[patent_issue_date] => 1998-09-08
[patent_title] => 'Cache module fault isolation techniques'
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Array
(
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[patent_issue_date] => 1999-03-09
[patent_title] => 'Digital write-and-read method and signal processing apparatus'
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Array
(
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Array
(
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[patent_title] => 'Semiconductor memory with test circuit'
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/732303 | Bit error measurement system | Feb 9, 1997 | Issued |
Array
(
[id] => 3970672
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/797606 | Storage unit and storage unit subsystem | Feb 6, 1997 | Issued |
Array
(
[id] => 3891108
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[patent_title] => 'Process control system for activating storage device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/796954 | Process control system for activating storage device | Feb 6, 1997 | Issued |
Array
(
[id] => 3826821
[patent_doc_number] => 05771243
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[patent_issue_date] => 1998-06-23
[patent_title] => 'Method of identifying redundant test patterns'
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Array
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[patent_title] => 'Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit'
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Array
(
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Array
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Array
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Array
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Array
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Array
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