
Vincent P. Canney
Examiner (ID: 8153)
| Most Active Art Unit | 2305 |
| Art Unit(s) | 2305, 2413, 2303, 2785, 2709, 2313, 2784, 2300 |
| Total Applications | 1739 |
| Issued Applications | 1512 |
| Pending Applications | 12 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3793477
[patent_doc_number] => 05818850
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Speed coverage tool and method'
[patent_app_type] => 1
[patent_app_number] => 8/773714
[patent_app_country] => US
[patent_app_date] => 1996-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4469
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/818/05818850.pdf
[firstpage_image] =>[orig_patent_app_number] => 773714
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/773714 | Speed coverage tool and method | Dec 19, 1996 | Issued |
Array
(
[id] => 3898538
[patent_doc_number] => 05715255
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Low overhead memory designs for IC terminals'
[patent_app_type] => 1
[patent_app_number] => 8/769971
[patent_app_country] => US
[patent_app_date] => 1996-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 47
[patent_no_of_words] => 11006
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/715/05715255.pdf
[firstpage_image] =>[orig_patent_app_number] => 769971
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/769971 | Low overhead memory designs for IC terminals | Dec 18, 1996 | Issued |
Array
(
[id] => 3784889
[patent_doc_number] => 05774471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Multiple location repair word line redundancy circuit'
[patent_app_type] => 1
[patent_app_number] => 8/767797
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5169
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774471.pdf
[firstpage_image] =>[orig_patent_app_number] => 767797
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767797 | Multiple location repair word line redundancy circuit | Dec 16, 1996 | Issued |
Array
(
[id] => 3765516
[patent_doc_number] => 05721741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Memory test system'
[patent_app_type] => 1
[patent_app_number] => 8/767393
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3150
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721741.pdf
[firstpage_image] =>[orig_patent_app_number] => 767393
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767393 | Memory test system | Dec 15, 1996 | Issued |
Array
(
[id] => 3697897
[patent_doc_number] => 05696768
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Method and apparatus for data storage array tracking'
[patent_app_type] => 1
[patent_app_number] => 8/763963
[patent_app_country] => US
[patent_app_date] => 1996-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3300
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696768.pdf
[firstpage_image] =>[orig_patent_app_number] => 763963
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763963 | Method and apparatus for data storage array tracking | Dec 9, 1996 | Issued |
Array
(
[id] => 3844845
[patent_doc_number] => 05740183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Method and apparatus for the operational verification of a microprocessor in the presence of interrupts'
[patent_app_type] => 1
[patent_app_number] => 8/761005
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6754
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/740/05740183.pdf
[firstpage_image] =>[orig_patent_app_number] => 761005
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761005 | Method and apparatus for the operational verification of a microprocessor in the presence of interrupts | Dec 4, 1996 | Issued |
Array
(
[id] => 3698748
[patent_doc_number] => 05691990
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Hybrid partial scan method'
[patent_app_type] => 1
[patent_app_number] => 8/759286
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3040
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/691/05691990.pdf
[firstpage_image] =>[orig_patent_app_number] => 759286
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759286 | Hybrid partial scan method | Dec 1, 1996 | Issued |
Array
(
[id] => 3698203
[patent_doc_number] => 05696788
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Circuit for searching fault location in a device having a plurality of application specific integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/758004
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 2530
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696788.pdf
[firstpage_image] =>[orig_patent_app_number] => 758004
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758004 | Circuit for searching fault location in a device having a plurality of application specific integrated circuits | Nov 26, 1996 | Issued |
Array
(
[id] => 3791827
[patent_doc_number] => 05757817
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Memory controller having automatic RAM detection'
[patent_app_type] => 1
[patent_app_number] => 8/757253
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4644
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/757/05757817.pdf
[firstpage_image] =>[orig_patent_app_number] => 757253
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757253 | Memory controller having automatic RAM detection | Nov 26, 1996 | Issued |
Array
(
[id] => 3890725
[patent_doc_number] => 05825783
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Semiconductor integrated circuit device with large-scale memory and controller embedded on one semiconductor chip and method of testing the device'
[patent_app_type] => 1
[patent_app_number] => 8/757287
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 7981
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825783.pdf
[firstpage_image] =>[orig_patent_app_number] => 757287
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757287 | Semiconductor integrated circuit device with large-scale memory and controller embedded on one semiconductor chip and method of testing the device | Nov 26, 1996 | Issued |
Array
(
[id] => 3894078
[patent_doc_number] => 05748644
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Method and apparatus for producing self-diagnostic information from a circuit board'
[patent_app_type] => 1
[patent_app_number] => 8/756845
[patent_app_country] => US
[patent_app_date] => 1996-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 3426
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748644.pdf
[firstpage_image] =>[orig_patent_app_number] => 756845
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756845 | Method and apparatus for producing self-diagnostic information from a circuit board | Nov 25, 1996 | Issued |
Array
(
[id] => 3773357
[patent_doc_number] => 05742614
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Apparatus and method for a variable step address generator'
[patent_app_type] => 1
[patent_app_number] => 8/756313
[patent_app_country] => US
[patent_app_date] => 1996-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2285
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742614.pdf
[firstpage_image] =>[orig_patent_app_number] => 756313
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756313 | Apparatus and method for a variable step address generator | Nov 24, 1996 | Issued |
| 08/751358 | METHOD AND CIRCUIT FOR TESTING A SEMICONDUCTOR MEMORY DEVICE OPERATING AT HIGH FREQUENCY | Nov 17, 1996 | Abandoned |
Array
(
[id] => 3802685
[patent_doc_number] => 05726820
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'Apparatus for recording or erasing image signals in sequence'
[patent_app_type] => 1
[patent_app_number] => 8/747747
[patent_app_country] => US
[patent_app_date] => 1996-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2837
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/726/05726820.pdf
[firstpage_image] =>[orig_patent_app_number] => 747747
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/747747 | Apparatus for recording or erasing image signals in sequence | Nov 11, 1996 | Issued |
Array
(
[id] => 3741733
[patent_doc_number] => 05666367
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Method for simulating a circuit'
[patent_app_type] => 1
[patent_app_number] => 8/745976
[patent_app_country] => US
[patent_app_date] => 1996-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 3914
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/666/05666367.pdf
[firstpage_image] =>[orig_patent_app_number] => 745976
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/745976 | Method for simulating a circuit | Nov 7, 1996 | Issued |
Array
(
[id] => 3844763
[patent_doc_number] => 05740177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Method of correcting error, suitable for storage device'
[patent_app_type] => 1
[patent_app_number] => 8/740899
[patent_app_country] => US
[patent_app_date] => 1996-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2496
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/740/05740177.pdf
[firstpage_image] =>[orig_patent_app_number] => 740899
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/740899 | Method of correcting error, suitable for storage device | Nov 3, 1996 | Issued |
Array
(
[id] => 3997290
[patent_doc_number] => 05862314
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'System and method for remapping defective memory locations'
[patent_app_type] => 1
[patent_app_number] => 8/741603
[patent_app_country] => US
[patent_app_date] => 1996-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3231
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/862/05862314.pdf
[firstpage_image] =>[orig_patent_app_number] => 741603
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741603 | System and method for remapping defective memory locations | Oct 31, 1996 | Issued |
Array
(
[id] => 3899965
[patent_doc_number] => 05724366
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/738655
[patent_app_country] => US
[patent_app_date] => 1996-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 94
[patent_no_of_words] => 18836
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/724/05724366.pdf
[firstpage_image] =>[orig_patent_app_number] => 738655
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/738655 | Semiconductor memory device | Oct 29, 1996 | Issued |
Array
(
[id] => 3826793
[patent_doc_number] => 05771241
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Method and apparatus for embedding operand synthesizing sequences in randomly generated tests'
[patent_app_type] => 1
[patent_app_number] => 8/741483
[patent_app_country] => US
[patent_app_date] => 1996-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 4664
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/771/05771241.pdf
[firstpage_image] =>[orig_patent_app_number] => 741483
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741483 | Method and apparatus for embedding operand synthesizing sequences in randomly generated tests | Oct 29, 1996 | Issued |
Array
(
[id] => 3734022
[patent_doc_number] => 05701308
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'Fast bist architecture with flexible standard interface'
[patent_app_type] => 1
[patent_app_number] => 8/739426
[patent_app_country] => US
[patent_app_date] => 1996-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6296
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/701/05701308.pdf
[firstpage_image] =>[orig_patent_app_number] => 739426
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/739426 | Fast bist architecture with flexible standard interface | Oct 28, 1996 | Issued |