Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3868293 [patent_doc_number] => 05768287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Apparatus and method for programming multistate memory device' [patent_app_type] => 1 [patent_app_number] => 8/735915 [patent_app_country] => US [patent_app_date] => 1996-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8550 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768287.pdf [firstpage_image] =>[orig_patent_app_number] => 735915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735915
Apparatus and method for programming multistate memory device Oct 23, 1996 Issued
Array ( [id] => 3791813 [patent_doc_number] => 05757816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'IDDQ testing of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/736623 [patent_app_country] => US [patent_app_date] => 1996-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5990 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757816.pdf [firstpage_image] =>[orig_patent_app_number] => 736623 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/736623
IDDQ testing of integrated circuits Oct 23, 1996 Issued
Array ( [id] => 3742597 [patent_doc_number] => 05694402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'System and method for structurally testing integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/735294 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694402.pdf [firstpage_image] =>[orig_patent_app_number] => 735294 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735294
System and method for structurally testing integrated circuit devices Oct 21, 1996 Issued
Array ( [id] => 3914200 [patent_doc_number] => 05751725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method and apparatus for determining the rate of received data in a variable rate communication system' [patent_app_type] => 1 [patent_app_number] => 8/730863 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6899 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751725.pdf [firstpage_image] =>[orig_patent_app_number] => 730863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730863
Method and apparatus for determining the rate of received data in a variable rate communication system Oct 17, 1996 Issued
Array ( [id] => 3698627 [patent_doc_number] => 05663964 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Method for testing digital memory devices' [patent_app_type] => 1 [patent_app_number] => 8/676335 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1052 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663964.pdf [firstpage_image] =>[orig_patent_app_number] => 676335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/676335
Method for testing digital memory devices Oct 9, 1996 Issued
Array ( [id] => 3891144 [patent_doc_number] => 05729554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Speculative execution of test patterns in a random test generator' [patent_app_type] => 1 [patent_app_number] => 8/720604 [patent_app_country] => US [patent_app_date] => 1996-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8340 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729554.pdf [firstpage_image] =>[orig_patent_app_number] => 720604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/720604
Speculative execution of test patterns in a random test generator Sep 30, 1996 Issued
Array ( [id] => 4046219 [patent_doc_number] => 05856984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Method of and system for generating test cases' [patent_app_type] => 1 [patent_app_number] => 8/722404 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4916 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856984.pdf [firstpage_image] =>[orig_patent_app_number] => 722404 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/722404
Method of and system for generating test cases Sep 29, 1996 Issued
Array ( [id] => 3631870 [patent_doc_number] => 05689514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Method and apparatus for testing the address system of a memory system' [patent_app_type] => 1 [patent_app_number] => 8/724573 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3126 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689514.pdf [firstpage_image] =>[orig_patent_app_number] => 724573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724573
Method and apparatus for testing the address system of a memory system Sep 29, 1996 Issued
Array ( [id] => 3704438 [patent_doc_number] => 05661730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Same state and opposite state diagnostic test for ferroelectric memories' [patent_app_type] => 1 [patent_app_number] => 8/723935 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661730.pdf [firstpage_image] =>[orig_patent_app_number] => 723935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723935
Same state and opposite state diagnostic test for ferroelectric memories Sep 26, 1996 Issued
Array ( [id] => 3898552 [patent_doc_number] => 05715256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Method and apparatus for handling multiplexer contention during scan' [patent_app_type] => 1 [patent_app_number] => 8/721445 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5343 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715256.pdf [firstpage_image] =>[orig_patent_app_number] => 721445 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721445
Method and apparatus for handling multiplexer contention during scan Sep 26, 1996 Issued
Array ( [id] => 3837059 [patent_doc_number] => 05732089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Bit error measurement circuit' [patent_app_type] => 1 [patent_app_number] => 8/721059 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6104 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732089.pdf [firstpage_image] =>[orig_patent_app_number] => 721059 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721059
Bit error measurement circuit Sep 25, 1996 Issued
Array ( [id] => 4170311 [patent_doc_number] => 06019502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Test circuits and methods for built-in testing integrated devices' [patent_app_type] => 1 [patent_app_number] => 8/717695 [patent_app_country] => US [patent_app_date] => 1996-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3015 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/019/06019502.pdf [firstpage_image] =>[orig_patent_app_number] => 717695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/717695
Test circuits and methods for built-in testing integrated devices Sep 22, 1996 Issued
Array ( [id] => 3781562 [patent_doc_number] => 05734661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Method and apparatus for providing external access to internal integrated circuit test circuits' [patent_app_type] => 1 [patent_app_number] => 8/717133 [patent_app_country] => US [patent_app_date] => 1996-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4614 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734661.pdf [firstpage_image] =>[orig_patent_app_number] => 717133 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/717133
Method and apparatus for providing external access to internal integrated circuit test circuits Sep 19, 1996 Issued
Array ( [id] => 3859414 [patent_doc_number] => 05719880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'On-chip operation for memories' [patent_app_type] => 1 [patent_app_number] => 8/710606 [patent_app_country] => US [patent_app_date] => 1996-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4191 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719880.pdf [firstpage_image] =>[orig_patent_app_number] => 710606 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710606
On-chip operation for memories Sep 19, 1996 Issued
Array ( [id] => 3874568 [patent_doc_number] => 05796746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Device and method for testing integrated circuit dice in an integrated circuit module' [patent_app_type] => 1 [patent_app_number] => 8/718173 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 5874 [patent_no_of_claims] => 109 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796746.pdf [firstpage_image] =>[orig_patent_app_number] => 718173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718173
Device and method for testing integrated circuit dice in an integrated circuit module Sep 18, 1996 Issued
Array ( [id] => 3829131 [patent_doc_number] => 05812754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Raid system with fibre channel arbitrated loop' [patent_app_type] => 1 [patent_app_number] => 8/718743 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4430 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812754.pdf [firstpage_image] =>[orig_patent_app_number] => 718743 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718743
Raid system with fibre channel arbitrated loop Sep 17, 1996 Issued
Array ( [id] => 3733967 [patent_doc_number] => 05701304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method for correcting unrecoverable sectors using track level redundancy in a disc drive storage system' [patent_app_type] => 1 [patent_app_number] => 8/714749 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 13492 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701304.pdf [firstpage_image] =>[orig_patent_app_number] => 714749 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714749
Method for correcting unrecoverable sectors using track level redundancy in a disc drive storage system Sep 15, 1996 Issued
Array ( [id] => 3894025 [patent_doc_number] => 05748640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Technique for incorporating a built-in self-test (BIST) of a DRAM block with existing functional test vectors for a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/711864 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4010 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748640.pdf [firstpage_image] =>[orig_patent_app_number] => 711864 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711864
Technique for incorporating a built-in self-test (BIST) of a DRAM block with existing functional test vectors for a microprocessor Sep 11, 1996 Issued
Array ( [id] => 3734008 [patent_doc_number] => 05701307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Low overhead input and output boundary scan cells' [patent_app_type] => 1 [patent_app_number] => 8/711137 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 9728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701307.pdf [firstpage_image] =>[orig_patent_app_number] => 711137 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711137
Low overhead input and output boundary scan cells Sep 8, 1996 Issued
Array ( [id] => 3838716 [patent_doc_number] => 05784384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Flip-flop circuit, scan path and storage circuit' [patent_app_type] => 1 [patent_app_number] => 8/708734 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 113 [patent_no_of_words] => 37608 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784384.pdf [firstpage_image] =>[orig_patent_app_number] => 708734 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708734
Flip-flop circuit, scan path and storage circuit Sep 4, 1996 Issued
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