
Vincent P. Canney
Examiner (ID: 2111)
| Most Active Art Unit | 2305 |
| Art Unit(s) | 2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413 |
| Total Applications | 1739 |
| Issued Applications | 1512 |
| Pending Applications | 12 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3868293
[patent_doc_number] => 05768287
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Apparatus and method for programming multistate memory device'
[patent_app_type] => 1
[patent_app_number] => 8/735915
[patent_app_country] => US
[patent_app_date] => 1996-10-24
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[pdf_file] => patents/05/768/05768287.pdf
[firstpage_image] =>[orig_patent_app_number] => 735915
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Array
(
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[patent_doc_number] => 05757816
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[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'IDDQ testing of integrated circuits'
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[patent_app_number] => 8/736623
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/736623 | IDDQ testing of integrated circuits | Oct 23, 1996 | Issued |
Array
(
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[patent_issue_date] => 1997-12-02
[patent_title] => 'System and method for structurally testing integrated circuit devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/735294 | System and method for structurally testing integrated circuit devices | Oct 21, 1996 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Method and apparatus for determining the rate of received data in a variable rate communication system'
[patent_app_type] => 1
[patent_app_number] => 8/730863
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[patent_app_date] => 1996-10-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730863 | Method and apparatus for determining the rate of received data in a variable rate communication system | Oct 17, 1996 | Issued |
Array
(
[id] => 3698627
[patent_doc_number] => 05663964
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Method for testing digital memory devices'
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[patent_app_number] => 8/676335
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Array
(
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[patent_issue_date] => 1998-03-17
[patent_title] => 'Speculative execution of test patterns in a random test generator'
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[firstpage_image] =>[orig_patent_app_number] => 720604
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/720604 | Speculative execution of test patterns in a random test generator | Sep 30, 1996 | Issued |
Array
(
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[patent_issue_date] => 1999-01-05
[patent_title] => 'Method of and system for generating test cases'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/722404 | Method of and system for generating test cases | Sep 29, 1996 | Issued |
Array
(
[id] => 3631870
[patent_doc_number] => 05689514
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[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'Method and apparatus for testing the address system of a memory system'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/724573 | Method and apparatus for testing the address system of a memory system | Sep 29, 1996 | Issued |
Array
(
[id] => 3704438
[patent_doc_number] => 05661730
[patent_country] => US
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[patent_issue_date] => 1997-08-26
[patent_title] => 'Same state and opposite state diagnostic test for ferroelectric memories'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/723935 | Same state and opposite state diagnostic test for ferroelectric memories | Sep 26, 1996 | Issued |
Array
(
[id] => 3898552
[patent_doc_number] => 05715256
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[patent_issue_date] => 1998-02-03
[patent_title] => 'Method and apparatus for handling multiplexer contention during scan'
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[pdf_file] => patents/05/715/05715256.pdf
[firstpage_image] =>[orig_patent_app_number] => 721445
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/721445 | Method and apparatus for handling multiplexer contention during scan | Sep 26, 1996 | Issued |
Array
(
[id] => 3837059
[patent_doc_number] => 05732089
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Bit error measurement circuit'
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[pdf_file] => patents/05/732/05732089.pdf
[firstpage_image] =>[orig_patent_app_number] => 721059
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/721059 | Bit error measurement circuit | Sep 25, 1996 | Issued |
Array
(
[id] => 4170311
[patent_doc_number] => 06019502
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[patent_issue_date] => 2000-02-01
[patent_title] => 'Test circuits and methods for built-in testing integrated devices'
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Array
(
[id] => 3781562
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/717133 | Method and apparatus for providing external access to internal integrated circuit test circuits | Sep 19, 1996 | Issued |
Array
(
[id] => 3859414
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Array
(
[id] => 3874568
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[patent_issue_date] => 1998-08-18
[patent_title] => 'Device and method for testing integrated circuit dice in an integrated circuit module'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/718173 | Device and method for testing integrated circuit dice in an integrated circuit module | Sep 18, 1996 | Issued |
Array
(
[id] => 3829131
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[patent_title] => 'Raid system with fibre channel arbitrated loop'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/718743 | Raid system with fibre channel arbitrated loop | Sep 17, 1996 | Issued |
Array
(
[id] => 3733967
[patent_doc_number] => 05701304
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[patent_title] => 'Method for correcting unrecoverable sectors using track level redundancy in a disc drive storage system'
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Array
(
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Array
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