Vincent P. Canney

Array ( [id] => 3844776 [patent_doc_number] => 05740178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Software for controlling a reliable backup memory' [patent_app_type] => 1 [patent_app_number] => 8/703144 [patent_app_country] => US [patent_app_date] => 1996-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2936 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740178.pdf [firstpage_image] =>[orig_patent_app_number] => 703144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3667477 [patent_doc_number] => 05659549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Memory test system having a pattern generator for a multi-bit test' [patent_app_type] => 1 [patent_app_number] => 8/702929 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4318 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659549.pdf [firstpage_image] =>[orig_patent_app_number] => 702929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3757623 [patent_doc_number] => 05717694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Fail analysis device for semiconductor memory test system' [patent_app_type] => 1 [patent_app_number] => 8/701699 [patent_app_country] => US [patent_app_date] => 1996-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3114 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717694.pdf [firstpage_image] =>[orig_patent_app_number] => 701699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3675136 [patent_doc_number] => 05668816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Method and apparatus for injecting errors into an array built-in self-test' [patent_app_type] => 1 [patent_app_number] => 8/697036 [patent_app_country] => US [patent_app_date] => 1996-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1799 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668816.pdf [firstpage_image] =>[orig_patent_app_number] => 697036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3805497 [patent_doc_number] => 05727006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Apparatus and method for detecting and correcting reverse polarity, in a packet-based data communications system' [patent_app_type] => 1 [patent_app_number] => 8/698374 [patent_app_country] => US [patent_app_date] => 1996-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 20172 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727006.pdf [firstpage_image] =>[orig_patent_app_number] => 698374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3675122 [patent_doc_number] => 05668815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Method for testing integrated memory using an integrated DMA controller' [patent_app_type] => 1 [patent_app_number] => 8/696734 [patent_app_country] => US [patent_app_date] => 1996-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11510 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668815.pdf [firstpage_image] =>[orig_patent_app_number] => 696734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3757722 [patent_doc_number] => 05717701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Apparatus and method for testing interconnections between semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/702414 [patent_app_country] => US [patent_app_date] => 1996-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5968 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717701.pdf [firstpage_image] =>[orig_patent_app_number] => 702414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3874611 [patent_doc_number] => 05796750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Method for programming a programmable logic device in an automatic tester' [patent_app_type] => 1 [patent_app_number] => 8/696444 [patent_app_country] => US [patent_app_date] => 1996-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4049 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796750.pdf [firstpage_image] =>[orig_patent_app_number] => 696444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3733844 [patent_doc_number] => 05673275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Accelerated mode tester timing' [patent_app_type] => 1 [patent_app_number] => 8/696346 [patent_app_country] => US [patent_app_date] => 1996-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6682 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673275.pdf [firstpage_image] =>[orig_patent_app_number] => 696346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3704029 [patent_doc_number] => 05651012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Implementation of half-path joining in a system for global performance analysis of a latch-based design' [patent_app_type] => 1 [patent_app_number] => 8/700596 [patent_app_country] => US [patent_app_date] => 1996-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7960 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/651/05651012.pdf [firstpage_image] =>[orig_patent_app_number] => 700596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3914372 [patent_doc_number] => 05751736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Testable electronic system' [patent_app_type] => 1 [patent_app_number] => 8/694595 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3520 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751736.pdf [firstpage_image] =>[orig_patent_app_number] => 694595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3675166 [patent_doc_number] => 05668818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'System and method for scan control of a programmable fuse circuit in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/692736 [patent_app_country] => US [patent_app_date] => 1996-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5239 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668818.pdf [firstpage_image] =>[orig_patent_app_number] => 692736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3742652 [patent_doc_number] => 05694406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Parallel associative processor formed from modified dram' [patent_app_type] => 1 [patent_app_number] => 8/695125 [patent_app_country] => US [patent_app_date] => 1996-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694406.pdf [firstpage_image] =>[orig_patent_app_number] => 695125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3658501 [patent_doc_number] => 05640404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Limited probes device testing for high pin count digital devices' [patent_app_type] => 1 [patent_app_number] => 8/693853 [patent_app_country] => US [patent_app_date] => 1996-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5083 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640404.pdf [firstpage_image] =>[orig_patent_app_number] => 693853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3802326 [patent_doc_number] => 05737518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method and apparatus for testing an object management system' [patent_app_type] => 1 [patent_app_number] => 8/690580 [patent_app_country] => US [patent_app_date] => 1996-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8768 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737518.pdf [firstpage_image] =>[orig_patent_app_number] => 690580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3706045 [patent_doc_number] => 05619511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Dynamic scan circuit and method for using the same' [patent_app_type] => 1 [patent_app_number] => 8/692864 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619511.pdf [firstpage_image] =>[orig_patent_app_number] => 692864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3775480 [patent_doc_number] => 05742758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Password protecting ROM based utilities in an adapter ROM' [patent_app_type] => 1 [patent_app_number] => 8/681740 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7700 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742758.pdf [firstpage_image] =>[orig_patent_app_number] => 681740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3716550 [patent_doc_number] => 05654971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Electronic circuit or board tester and method of testing an electronic device' [patent_app_type] => 1 [patent_app_number] => 8/686794 [patent_app_country] => US [patent_app_date] => 1996-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5018 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654971.pdf [firstpage_image] =>[orig_patent_app_number] => 686794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3868572 [patent_doc_number] => 05706295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method of checking design rules for semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/686815 [patent_app_country] => US [patent_app_date] => 1996-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 5435 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706295.pdf [firstpage_image] =>[orig_patent_app_number] => 686815 [rel_patent_id] =>[rel_patent_doc_number] =>)