Search

Vincent P. Canney

Examiner (ID: 2111)

Most Active Art Unit
2305
Art Unit(s)
2709, 2784, 2313, 2305, 2785, 2300, 2303, 2413
Total Applications
1739
Issued Applications
1512
Pending Applications
12
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3698649 [patent_doc_number] => 05663966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'System and method for minimizing simultaneous switching during scan-based testing' [patent_app_type] => 1 [patent_app_number] => 8/686105 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7863 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663966.pdf [firstpage_image] =>[orig_patent_app_number] => 686105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/686105
System and method for minimizing simultaneous switching during scan-based testing Jul 23, 1996 Issued
Array ( [id] => 3893315 [patent_doc_number] => 05764888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Electronic micro identification circuit that is inherently bonded to someone or something' [patent_app_type] => 1 [patent_app_number] => 8/684520 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2446 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764888.pdf [firstpage_image] =>[orig_patent_app_number] => 684520 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684520
Electronic micro identification circuit that is inherently bonded to someone or something Jul 18, 1996 Issued
Array ( [id] => 3757695 [patent_doc_number] => 05717699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Method and apparatus for accessing internal integrated circuit signals' [patent_app_type] => 1 [patent_app_number] => 8/683484 [patent_app_country] => US [patent_app_date] => 1996-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4877 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717699.pdf [firstpage_image] =>[orig_patent_app_number] => 683484 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/683484
Method and apparatus for accessing internal integrated circuit signals Jul 17, 1996 Issued
Array ( [id] => 3870389 [patent_doc_number] => 05706422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method of locating fault of communication system' [patent_app_type] => 1 [patent_app_number] => 8/682012 [patent_app_country] => US [patent_app_date] => 1996-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4095 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706422.pdf [firstpage_image] =>[orig_patent_app_number] => 682012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/682012
Method of locating fault of communication system Jul 15, 1996 Issued
Array ( [id] => 3838864 [patent_doc_number] => 05732208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'External storage device and memory access control method thereof' [patent_app_type] => 1 [patent_app_number] => 8/679960 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 6908 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732208.pdf [firstpage_image] =>[orig_patent_app_number] => 679960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679960
External storage device and memory access control method thereof Jul 14, 1996 Issued
Array ( [id] => 3675150 [patent_doc_number] => 05668817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths' [patent_app_type] => 1 [patent_app_number] => 8/680314 [patent_app_country] => US [patent_app_date] => 1996-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668817.pdf [firstpage_image] =>[orig_patent_app_number] => 680314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/680314
Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths Jul 10, 1996 Issued
Array ( [id] => 3790601 [patent_doc_number] => 05809035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Method and apparatus to apply prioritization policy in electronic systems' [patent_app_type] => 1 [patent_app_number] => 8/677058 [patent_app_country] => US [patent_app_date] => 1996-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 7394 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809035.pdf [firstpage_image] =>[orig_patent_app_number] => 677058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677058
Method and apparatus to apply prioritization policy in electronic systems Jul 8, 1996 Issued
Array ( [id] => 3914400 [patent_doc_number] => 05751738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Pattern generator cicuit for semiconductor test systerm' [patent_app_type] => 1 [patent_app_number] => 8/677016 [patent_app_country] => US [patent_app_date] => 1996-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3120 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751738.pdf [firstpage_image] =>[orig_patent_app_number] => 677016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677016
Pattern generator cicuit for semiconductor test systerm Jul 7, 1996 Issued
Array ( [id] => 3742611 [patent_doc_number] => 05694403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'System and method for sequential vector compaction in the presence of multiple three-state busses' [patent_app_type] => 1 [patent_app_number] => 8/679465 [patent_app_country] => US [patent_app_date] => 1996-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3005 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694403.pdf [firstpage_image] =>[orig_patent_app_number] => 679465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679465
System and method for sequential vector compaction in the presence of multiple three-state busses Jul 2, 1996 Issued
Array ( [id] => 3892587 [patent_doc_number] => 05799022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Faulty module location in a fault tolerant computer system' [patent_app_type] => 1 [patent_app_number] => 8/675264 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6668 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799022.pdf [firstpage_image] =>[orig_patent_app_number] => 675264 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/675264
Faulty module location in a fault tolerant computer system Jun 30, 1996 Issued
Array ( [id] => 3799641 [patent_doc_number] => 05737340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Multi-phase test point insertion for built-in self test of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/678376 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8395 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737340.pdf [firstpage_image] =>[orig_patent_app_number] => 678376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678376
Multi-phase test point insertion for built-in self test of integrated circuits Jun 30, 1996 Issued
Array ( [id] => 3707374 [patent_doc_number] => 05677913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method and apparatus for efficient self testing of on-chip memory' [patent_app_type] => 1 [patent_app_number] => 8/674354 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4242 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677913.pdf [firstpage_image] =>[orig_patent_app_number] => 674354 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674354
Method and apparatus for efficient self testing of on-chip memory Jun 30, 1996 Issued
Array ( [id] => 3906362 [patent_doc_number] => 05835502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme' [patent_app_type] => 1 [patent_app_number] => 8/673258 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4761 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835502.pdf [firstpage_image] =>[orig_patent_app_number] => 673258 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673258
Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme Jun 27, 1996 Issued
Array ( [id] => 3630353 [patent_doc_number] => 05642364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Contactless testing of inputs and outputs of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/678384 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3268 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642364.pdf [firstpage_image] =>[orig_patent_app_number] => 678384 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678384
Contactless testing of inputs and outputs of integrated circuits Jun 27, 1996 Issued
Array ( [id] => 3631899 [patent_doc_number] => 05689516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Reset circuit for a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/670916 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4341 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689516.pdf [firstpage_image] =>[orig_patent_app_number] => 670916 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/670916
Reset circuit for a programmable logic device Jun 25, 1996 Issued
Array ( [id] => 3657815 [patent_doc_number] => 05629944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Test mode setting circuit of test circuit for semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/670823 [patent_app_country] => US [patent_app_date] => 1996-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4206 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629944.pdf [firstpage_image] =>[orig_patent_app_number] => 670823 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/670823
Test mode setting circuit of test circuit for semiconductor memory Jun 24, 1996 Issued
Array ( [id] => 3791798 [patent_doc_number] => 05757815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Semiconductor memory test system' [patent_app_type] => 1 [patent_app_number] => 8/667655 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3321 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757815.pdf [firstpage_image] =>[orig_patent_app_number] => 667655 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/667655
Semiconductor memory test system Jun 20, 1996 Issued
Array ( [id] => 3899925 [patent_doc_number] => 05724363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Optical analog signal transmission system' [patent_app_type] => 1 [patent_app_number] => 8/667413 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 468 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724363.pdf [firstpage_image] =>[orig_patent_app_number] => 667413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/667413
Optical analog signal transmission system Jun 20, 1996 Issued
Array ( [id] => 3844818 [patent_doc_number] => 05740181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and apparatus for at speed observability of pipelined circuits' [patent_app_type] => 1 [patent_app_number] => 8/662403 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2583 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740181.pdf [firstpage_image] =>[orig_patent_app_number] => 662403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662403
Method and apparatus for at speed observability of pipelined circuits Jun 11, 1996 Issued
Array ( [id] => 3855168 [patent_doc_number] => 05745498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Rapid compare of two binary numbers' [patent_app_type] => 1 [patent_app_number] => 8/661575 [patent_app_country] => US [patent_app_date] => 1996-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8176 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745498.pdf [firstpage_image] =>[orig_patent_app_number] => 661575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/661575
Rapid compare of two binary numbers Jun 10, 1996 Issued
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