Search

Vincent Q Nguyen

Examiner (ID: 15631, Phone: (571)272-2234 , Office: P/2866 )

Most Active Art Unit
2858
Art Unit(s)
2858, 2831, 2866
Total Applications
2410
Issued Applications
2104
Pending Applications
113
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19137818 [patent_doc_number] => 11972789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Memory device with error per row counter (EpRC) performing error check and scrub (ECS) [patent_app_type] => utility [patent_app_number] => 18/365317 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 10388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365317 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365317
Memory device with error per row counter (EpRC) performing error check and scrub (ECS) Aug 3, 2023 Issued
Array ( [id] => 18789021 [patent_doc_number] => 20230377629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SECOND WORD LINE COMBINED WITH Y-MUX SIGNAL IN HIGH VOLTAGE MEMORY PROGRAM [patent_app_type] => utility [patent_app_number] => 18/361559 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361559 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361559
SECOND WORD LINE COMBINED WITH Y-MUX SIGNAL IN HIGH VOLTAGE MEMORY PROGRAM Jul 27, 2023 Pending
Array ( [id] => 18926765 [patent_doc_number] => 20240029769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => Multi-Stage Bit Line Pre-Charge [patent_app_type] => utility [patent_app_number] => 18/359079 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359079
Multi-Stage Bit Line Pre-Charge Jul 25, 2023 Pending
Array ( [id] => 18729088 [patent_doc_number] => 20230343383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/218243 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218243 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218243
QUADRATURE ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME Jul 4, 2023 Pending
Array ( [id] => 18743092 [patent_doc_number] => 20230352080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SENSE AMPLIFIER WITH DIGIT LINE MULTIPLEXING [patent_app_type] => utility [patent_app_number] => 18/217205 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217205
SENSE AMPLIFIER WITH DIGIT LINE MULTIPLEXING Jun 29, 2023 Pending
Array ( [id] => 18696074 [patent_doc_number] => 20230326505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => MEMORY DEVICE FOR REDUCING ACTIVE POWER [patent_app_type] => utility [patent_app_number] => 18/336418 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336418
MEMORY DEVICE FOR REDUCING ACTIVE POWER Jun 15, 2023 Pending
Array ( [id] => 18599976 [patent_doc_number] => 20230274777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => MEMORY SUBWORD DRIVER CIRCUITS AND LAYOUT [patent_app_type] => utility [patent_app_number] => 18/313948 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313948
MEMORY SUBWORD DRIVER CIRCUITS AND LAYOUT May 7, 2023 Pending
Array ( [id] => 19260674 [patent_doc_number] => 12020739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Memory device for reducing row hammer disturbance, and a method of refreshing the same [patent_app_type] => utility [patent_app_number] => 18/138849 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9076 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138849
Memory device for reducing row hammer disturbance, and a method of refreshing the same Apr 24, 2023 Issued
Array ( [id] => 19168253 [patent_doc_number] => 11984164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells [patent_app_type] => utility [patent_app_number] => 18/300706 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300706
Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells Apr 13, 2023 Issued
Array ( [id] => 18488141 [patent_doc_number] => 20230215489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO IMPROVE READ MARGIN AND TO ALLEVIATE THE NEED FOR MANAGING DEMARCATION READ VOLTAGES [patent_app_type] => utility [patent_app_number] => 18/182305 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182305 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182305
Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages Mar 9, 2023 Issued
Array ( [id] => 18488140 [patent_doc_number] => 20230215488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => VARYING A TIME AVERAGE FOR FEEDBACK OF A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/120136 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120136
Varying a time average for feedback of a memory system Mar 9, 2023 Issued
Array ( [id] => 18439687 [patent_doc_number] => 20230186982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/164199 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164199
Semiconductor device for selectively performing isolation function and layout displacement method thereof Feb 2, 2023 Issued
Array ( [id] => 18439680 [patent_doc_number] => 20230186975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/105442 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105442
Apparatuses and methods for logic/memory devices Feb 2, 2023 Issued
Array ( [id] => 18967206 [patent_doc_number] => 11900984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Data destruction [patent_app_type] => utility [patent_app_number] => 18/104069 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104069
Data destruction Jan 30, 2023 Issued
Array ( [id] => 18439704 [patent_doc_number] => 20230186999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHOD FOR CHECKING THE ERASING PHASE OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/103226 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103226
Method for checking the erasing phase of a memory device Jan 29, 2023 Issued
Array ( [id] => 18379418 [patent_doc_number] => 20230154507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => BIT LINE LOGIC CIRCUITS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/153464 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153464
Bit line logic circuits and methods Jan 11, 2023 Issued
Array ( [id] => 18366427 [patent_doc_number] => 20230148018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => READ-TIME OVERHEAD AND POWER OPTIMIZATIONS WITH COMMAND QUEUES IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/095646 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095646
Read-time overhead and power optimizations with command queues in memory device Jan 10, 2023 Issued
Array ( [id] => 18295809 [patent_doc_number] => 20230105495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => Four-Poly-Pitch Sram Cell With Backside Metal Tracks [patent_app_type] => utility [patent_app_number] => 18/064859 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064859
Four-Poly-Pitch Sram Cell With Backside Metal Tracks Dec 11, 2022 Pending
Array ( [id] => 19062894 [patent_doc_number] => 11942139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Performing refresh operations on memory cells [patent_app_type] => utility [patent_app_number] => 18/075570 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075570
Performing refresh operations on memory cells Dec 5, 2022 Issued
Array ( [id] => 18268874 [patent_doc_number] => 20230090116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MEMORY DEVICE CAPABLE OF ADJUSTING CLOCK SIGNAL BASED ON OPERATING SPEED AND PROPAGATION DELAY OF COMMAND/ADDRESS SIGNAL [patent_app_type] => utility [patent_app_number] => 17/992651 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/992651
Memory device capable of adjusting clock signal based on operating speed and propagation delay of command/address signal Nov 21, 2022 Issued
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