
Vincent Wall
Examiner (ID: 12320, Phone: (571)272-9567 , Office: P/2893 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2898, 2893, 2822 |
| Total Applications | 944 |
| Issued Applications | 534 |
| Pending Applications | 123 |
| Abandoned Applications | 307 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14198615
[patent_doc_number] => 10266400
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => MEMS device with multi pressure
[patent_app_type] => utility
[patent_app_number] => 15/707470
[patent_app_country] => US
[patent_app_date] => 2017-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 6788
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707470
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/707470 | MEMS device with multi pressure | Sep 17, 2017 | Issued |
Array
(
[id] => 12129327
[patent_doc_number] => 20180012912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-11
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/697627
[patent_app_country] => US
[patent_app_date] => 2017-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 54
[patent_no_of_words] => 51514
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15697627
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/697627 | Semiconductor device | Sep 6, 2017 | Issued |
Array
(
[id] => 13709019
[patent_doc_number] => 20170365464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-21
[patent_title] => Compound Semiconductor Substrate and Method of Forming a Compound Semiconductor Substrate
[patent_app_type] => utility
[patent_app_number] => 15/690596
[patent_app_country] => US
[patent_app_date] => 2017-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3769
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690596
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/690596 | Compound semiconductor substrate and method of forming a compound semiconductor substrate | Aug 29, 2017 | Issued |
Array
(
[id] => 12223453
[patent_doc_number] => 20180061814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-01
[patent_title] => 'BACKLIGHT SYSTEM AND METHOD FOR MANUFACTURING THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/690170
[patent_app_country] => US
[patent_app_date] => 2017-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4221
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690170
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/690170 | BACKLIGHT SYSTEM AND METHOD FOR MANUFACTURING THEREOF | Aug 28, 2017 | Abandoned |
Array
(
[id] => 12650919
[patent_doc_number] => 20180108804
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-19
[patent_title] => PHOTON SOURCE AND A METHOD OF FABRICATING A PHOTON SOURCE
[patent_app_type] => utility
[patent_app_number] => 15/689230
[patent_app_country] => US
[patent_app_date] => 2017-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17289
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689230
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/689230 | PHOTON SOURCE AND A METHOD OF FABRICATING A PHOTON SOURCE | Aug 28, 2017 | Abandoned |
Array
(
[id] => 12122479
[patent_doc_number] => 20180006065
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 15/681254
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3497
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681254
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/681254 | Array substrate and display device and method for making the array substrate | Aug 17, 2017 | Issued |
Array
(
[id] => 12027176
[patent_doc_number] => 20170317275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-02
[patent_title] => 'PHASE-CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 15/654405
[patent_app_country] => US
[patent_app_date] => 2017-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4184
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654405
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/654405 | PHASE-CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE | Jul 18, 2017 | Abandoned |
Array
(
[id] => 12005486
[patent_doc_number] => 20170309642
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-26
[patent_title] => 'Systems and Methods for a Semiconductor Structure Having Multiple Semiconductor-Device Layers'
[patent_app_type] => utility
[patent_app_number] => 15/643544
[patent_app_country] => US
[patent_app_date] => 2017-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 4682
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643544
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/643544 | Systems and Methods for a Semiconductor Structure Having Multiple Semiconductor-Device Layers | Jul 6, 2017 | Abandoned |
Array
(
[id] => 13030881
[patent_doc_number] => 10038065
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-31
[patent_title] => Method of forming a semiconductor device with a gate contact positioned above the active region
[patent_app_type] => utility
[patent_app_number] => 15/639095
[patent_app_country] => US
[patent_app_date] => 2017-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 27
[patent_no_of_words] => 7091
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15639095
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/639095 | Method of forming a semiconductor device with a gate contact positioned above the active region | Jun 29, 2017 | Issued |
Array
(
[id] => 11997599
[patent_doc_number] => 20170301753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-19
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/640077
[patent_app_country] => US
[patent_app_date] => 2017-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 59
[patent_figures_cnt] => 59
[patent_no_of_words] => 19868
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640077
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/640077 | SEMICONDUCTOR DEVICE | Jun 29, 2017 | Abandoned |
Array
(
[id] => 16645541
[patent_doc_number] => 10923407
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/630934
[patent_app_country] => US
[patent_app_date] => 2017-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 6766
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 317
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630934
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/630934 | Semiconductor device | Jun 21, 2017 | Issued |
Array
(
[id] => 11946048
[patent_doc_number] => 20170250198
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-31
[patent_title] => 'METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE FORMING GATE REGIONS AND CORRESPONDING TRANSISTOR PRODUCED BY SAID METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/597337
[patent_app_country] => US
[patent_app_date] => 2017-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 13093
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597337
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/597337 | METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE FORMING GATE REGIONS AND CORRESPONDING TRANSISTOR PRODUCED BY SAID METHOD | May 16, 2017 | Abandoned |
Array
(
[id] => 13755019
[patent_doc_number] => 10170463
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Bipolar transistor compatible with vertical FET fabrication
[patent_app_type] => utility
[patent_app_number] => 15/596376
[patent_app_country] => US
[patent_app_date] => 2017-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 4233
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596376
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596376 | Bipolar transistor compatible with vertical FET fabrication | May 15, 2017 | Issued |
Array
(
[id] => 11945956
[patent_doc_number] => 20170250107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-31
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/594872
[patent_app_country] => US
[patent_app_date] => 2017-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 9313
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594872
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/594872 | SEMICONDUCTOR DEVICE | May 14, 2017 | Abandoned |
Array
(
[id] => 13667155
[patent_doc_number] => 10163755
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-25
[patent_title] => Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
[patent_app_type] => utility
[patent_app_number] => 15/498321
[patent_app_country] => US
[patent_app_date] => 2017-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 6566
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15498321
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/498321 | Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths | Apr 25, 2017 | Issued |
Array
(
[id] => 11718364
[patent_doc_number] => 20170186863
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-29
[patent_title] => 'Method of Producing an Integrated Power Transistor Circuit Having a Current-Measuring Cell'
[patent_app_type] => utility
[patent_app_number] => 15/458459
[patent_app_country] => US
[patent_app_date] => 2017-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5084
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15458459
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/458459 | Method of producing an integrated power transistor circuit having a current-measuring cell | Mar 13, 2017 | Issued |
Array
(
[id] => 14151831
[patent_doc_number] => 10256305
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-09
[patent_title] => High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices
[patent_app_type] => utility
[patent_app_number] => 15/449449
[patent_app_country] => US
[patent_app_date] => 2017-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4051
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449449
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/449449 | High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices | Mar 2, 2017 | Issued |
Array
(
[id] => 13404521
[patent_doc_number] => 20180253803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-06
[patent_title] => SYSTEMS AND PROCESSES FOR INDEPENDENT RECONCILING OF CRUDE OIL PURCHASE TRANSACTIONS
[patent_app_type] => utility
[patent_app_number] => 15/448224
[patent_app_country] => US
[patent_app_date] => 2017-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11018
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15448224
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/448224 | SYSTEMS AND PROCESSES FOR INDEPENDENT RECONCILING OF CRUDE OIL PURCHASE TRANSACTIONS | Mar 1, 2017 | Abandoned |
Array
(
[id] => 12595965
[patent_doc_number] => 20180090485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION
[patent_app_type] => utility
[patent_app_number] => 15/447865
[patent_app_country] => US
[patent_app_date] => 2017-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447865
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/447865 | Bipolar transistor compatible with vertical FET fabrication | Mar 1, 2017 | Issued |
Array
(
[id] => 12188710
[patent_doc_number] => 20180047646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-15
[patent_title] => 'ACCURACY IMPROVEMENTS IN OPTICAL METROLOGY'
[patent_app_type] => utility
[patent_app_number] => 15/540409
[patent_app_country] => US
[patent_app_date] => 2017-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 13368
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15540409
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/540409 | ACCURACY IMPROVEMENTS IN OPTICAL METROLOGY | Feb 22, 2017 | Abandoned |