
Vincent Wall
Examiner (ID: 17077, Phone: (571)272-9567 , Office: P/2893 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2893, 2822, 2898 |
| Total Applications | 914 |
| Issued Applications | 516 |
| Pending Applications | 121 |
| Abandoned Applications | 305 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10479365
[patent_doc_number] => 20150364382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-17
[patent_title] => 'BACK BIASED TRANSISTOR AND CURRENT SOURCE BIASING'
[patent_app_type] => utility
[patent_app_number] => 14/494297
[patent_app_country] => US
[patent_app_date] => 2014-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9182
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14494297
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/494297 | BACK BIASED TRANSISTOR AND CURRENT SOURCE BIASING | Sep 22, 2014 | Abandoned |
Array
(
[id] => 11026645
[patent_doc_number] => 20160223601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-04
[patent_title] => 'ENERGY MONITORING METHOD AND APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 15/022258
[patent_app_country] => US
[patent_app_date] => 2014-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3754
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15022258
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/022258 | ENERGY MONITORING METHOD AND APPARATUS | Sep 18, 2014 | Abandoned |
Array
(
[id] => 11094127
[patent_doc_number] => 20160291094
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-06
[patent_title] => 'METHOD FOR ESTIMATING THE AGEING OF A CELL OF A STORAGE BATTERY'
[patent_app_type] => utility
[patent_app_number] => 15/022360
[patent_app_country] => US
[patent_app_date] => 2014-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5454
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15022360
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/022360 | METHOD FOR ESTIMATING THE AGEING OF A CELL OF A STORAGE BATTERY | Sep 15, 2014 | Abandoned |
Array
(
[id] => 10418215
[patent_doc_number] => 20150303225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-22
[patent_title] => 'ARRAY SUBSTRATE, FABRICATION METHOD THEREOF AND DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/439999
[patent_app_country] => US
[patent_app_date] => 2014-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4939
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14439999
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/439999 | Array substrate, fabrication method thereof and display device | Sep 4, 2014 | Issued |
Array
(
[id] => 10718193
[patent_doc_number] => 20160064340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-03
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/471179
[patent_app_country] => US
[patent_app_date] => 2014-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 7921
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14471179
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/471179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Aug 27, 2014 | Abandoned |
Array
(
[id] => 11432132
[patent_doc_number] => 09570457
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-14
[patent_title] => 'Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates'
[patent_app_type] => utility
[patent_app_number] => 14/468410
[patent_app_country] => US
[patent_app_date] => 2014-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 6126
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468410
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/468410 | Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates | Aug 25, 2014 | Issued |
Array
(
[id] => 11012254
[patent_doc_number] => 20160209207
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-21
[patent_title] => 'BOARD INSPECTION METHOD AND BOARD INSPECTION SYSTEM USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/913740
[patent_app_country] => US
[patent_app_date] => 2014-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4635
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913740
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/913740 | BOARD INSPECTION METHOD AND BOARD INSPECTION SYSTEM USING THE SAME | Aug 24, 2014 | Abandoned |
Array
(
[id] => 11019262
[patent_doc_number] => 20160216215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-28
[patent_title] => 'SUBSTRATE INSPECTING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/913749
[patent_app_country] => US
[patent_app_date] => 2014-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4265
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913749
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/913749 | SUBSTRATE INSPECTING APPARATUS | Aug 24, 2014 | Abandoned |
Array
(
[id] => 14125593
[patent_doc_number] => 10249661
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Imaging devices with dummy patterns
[patent_app_type] => utility
[patent_app_number] => 14/466412
[patent_app_country] => US
[patent_app_date] => 2014-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4556
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466412
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/466412 | Imaging devices with dummy patterns | Aug 21, 2014 | Issued |
Array
(
[id] => 10710019
[patent_doc_number] => 20160056167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-25
[patent_title] => 'TUNGSTEN SEPARATION'
[patent_app_type] => utility
[patent_app_number] => 14/463561
[patent_app_country] => US
[patent_app_date] => 2014-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7710
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463561
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/463561 | Tungsten separation | Aug 18, 2014 | Issued |
Array
(
[id] => 10689576
[patent_doc_number] => 20160035723
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-04
[patent_title] => 'MACRO DESIGN OF DEVICE CHARACTERIZATION FOR 14NM AND BEYOND TECHNOLOGIES'
[patent_app_type] => utility
[patent_app_number] => 14/447193
[patent_app_country] => US
[patent_app_date] => 2014-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4341
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14447193
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/447193 | MACRO DESIGN OF DEVICE CHARACTERIZATION FOR 14NM AND BEYOND TECHNOLOGIES | Jul 29, 2014 | Abandoned |
Array
(
[id] => 13201889
[patent_doc_number] => 10115868
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-30
[patent_title] => Optoelectronic semiconductor chip, optoelectronic component, and method of producing semiconductor chips
[patent_app_type] => utility
[patent_app_number] => 14/906581
[patent_app_country] => US
[patent_app_date] => 2014-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 8152
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14906581
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/906581 | Optoelectronic semiconductor chip, optoelectronic component, and method of producing semiconductor chips | Jul 22, 2014 | Issued |
Array
(
[id] => 10673992
[patent_doc_number] => 20160020138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-21
[patent_title] => 'Techniques for Creating a Local Interconnect Using a SOI Wafer'
[patent_app_type] => utility
[patent_app_number] => 14/335328
[patent_app_country] => US
[patent_app_date] => 2014-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3913
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14335328
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/335328 | Techniques for creating a local interconnect using a SOI wafer | Jul 17, 2014 | Issued |
Array
(
[id] => 10817776
[patent_doc_number] => 20160163939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-09
[patent_title] => 'OPTOELECTRONIC SEMICONDUCTOR CHIP, SEMICONDUCTOR COMPONENT AND METHOD OF PRODUCING OPTOELECTRONIC SEMICONDUCTOR CHIPS'
[patent_app_type] => utility
[patent_app_number] => 14/906724
[patent_app_country] => US
[patent_app_date] => 2014-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5535
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14906724
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/906724 | OPTOELECTRONIC SEMICONDUCTOR CHIP, SEMICONDUCTOR COMPONENT AND METHOD OF PRODUCING OPTOELECTRONIC SEMICONDUCTOR CHIPS | Jul 16, 2014 | Abandoned |
Array
(
[id] => 10667028
[patent_doc_number] => 20160013173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-14
[patent_title] => 'METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS'
[patent_app_type] => utility
[patent_app_number] => 14/330805
[patent_app_country] => US
[patent_app_date] => 2014-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6722
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330805
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/330805 | Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths | Jul 13, 2014 | Issued |
Array
(
[id] => 11353802
[patent_doc_number] => 20160372542
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2016-12-22
[patent_title] => 'TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 14/329936
[patent_app_country] => US
[patent_app_date] => 2014-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 2732
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329936
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/329936 | TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS | Jul 11, 2014 | Abandoned |
Array
(
[id] => 11353802
[patent_doc_number] => 20160372542
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2016-12-22
[patent_title] => 'TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 14/329936
[patent_app_country] => US
[patent_app_date] => 2014-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 2732
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329936
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/329936 | TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS | Jul 11, 2014 | Abandoned |
Array
(
[id] => 10440683
[patent_doc_number] => 20150325695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'SEMICONDUCTOR APPARATUS, METHOD FOR FABRICATING THE SAME, AND VARIABLE RESISTIVE MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/329555
[patent_app_country] => US
[patent_app_date] => 2014-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4081
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329555
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/329555 | SEMICONDUCTOR APPARATUS, METHOD FOR FABRICATING THE SAME, AND VARIABLE RESISTIVE MEMORY DEVICE | Jul 10, 2014 | Abandoned |
Array
(
[id] => 10916557
[patent_doc_number] => 20140319576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-30
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/327288
[patent_app_country] => US
[patent_app_date] => 2014-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 9207
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327288
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/327288 | SEMICONDUCTOR DEVICE | Jul 8, 2014 | Abandoned |
Array
(
[id] => 10286152
[patent_doc_number] => 20150171150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'MANUFACTURING METHOD OF ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/327111
[patent_app_country] => US
[patent_app_date] => 2014-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4447
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327111
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/327111 | MANUFACTURING METHOD OF ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE | Jul 8, 2014 | Abandoned |