
Vincent Wall
Examiner (ID: 17077, Phone: (571)272-9567 , Office: P/2893 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2893, 2822, 2898 |
| Total Applications | 914 |
| Issued Applications | 516 |
| Pending Applications | 121 |
| Abandoned Applications | 305 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9895553
[patent_doc_number] => 20150050752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-19
[patent_title] => 'METHODS FOR CLEANING A WAFER EDGE INCLUDING A NOTCH'
[patent_app_type] => utility
[patent_app_number] => 13/967160
[patent_app_country] => US
[patent_app_date] => 2013-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967160
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/967160 | METHODS FOR CLEANING A WAFER EDGE INCLUDING A NOTCH | Aug 13, 2013 | Abandoned |
Array
(
[id] => 9432920
[patent_doc_number] => 20140110826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-24
[patent_title] => 'BACKSIDE PROTECTION FOR A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP)'
[patent_app_type] => utility
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[patent_app_date] => 2013-08-14
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/966506 | BACKSIDE PROTECTION FOR A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) | Aug 13, 2013 | Abandoned |
Array
(
[id] => 9895592
[patent_doc_number] => 20150050792
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[patent_kind] => A1
[patent_issue_date] => 2015-02-19
[patent_title] => 'EXTRA NARROW DIFFUSION BREAK FOR 3D FINFET TECHNOLOGIES'
[patent_app_type] => utility
[patent_app_number] => 13/965258
[patent_app_country] => US
[patent_app_date] => 2013-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/965258 | EXTRA NARROW DIFFUSION BREAK FOR 3D FINFET TECHNOLOGIES | Aug 12, 2013 | Abandoned |
Array
(
[id] => 9895552
[patent_doc_number] => 20150050751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-19
[patent_title] => 'METHOD OF CONTROLLING THRESHOLD VOLTAGE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/965600
[patent_app_country] => US
[patent_app_date] => 2013-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/965600 | Method of controlling threshold voltage and method of fabricating semiconductor device | Aug 12, 2013 | Issued |
Array
(
[id] => 9864851
[patent_doc_number] => 20150044870
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[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A SELF-ALIGNED OPL REPLACEMENT CONTACT AND PATTERNED HSQ AND A SEMICONDUCTOR DEVICE FORMED BY SAME'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/964286 | Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ and a semiconductor device formed by same | Aug 11, 2013 | Issued |
Array
(
[id] => 10395160
[patent_doc_number] => 20150280167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'PACKAGING COVER PLATE FOR ORGANIC LIGHT-EMITTING DEVICE, ORGANIC LIGHT-EMITTING DEVICE AND DISPLAY DEVICE HAVING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/236303
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Array
(
[id] => 9864823
[patent_doc_number] => 20150044842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'Integrating Junction Formation of Transistors with Contact Formation'
[patent_app_type] => utility
[patent_app_number] => 13/963911
[patent_app_country] => US
[patent_app_date] => 2013-08-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/963911 | Integrating junction formation of transistors with contact formation | Aug 8, 2013 | Issued |
Array
(
[id] => 9785806
[patent_doc_number] => 20140302626
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[patent_issue_date] => 2014-10-09
[patent_title] => 'METHOD OF MANUFACTURING DISPLAY AND DEPOSITION APPARATUS FOR THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/964020
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Array
(
[id] => 11221850
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[patent_issue_date] => 2016-09-20
[patent_title] => 'Method of forming nano crystals and method of manufacturing organic light-emitting display apparatus including thin film having the same'
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[patent_app_number] => 13/963662
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Array
(
[id] => 9864812
[patent_doc_number] => 20150044831
[patent_country] => US
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[patent_issue_date] => 2015-02-12
[patent_title] => 'SEMICONDUCTOR PROCESS'
[patent_app_type] => utility
[patent_app_number] => 13/962959
[patent_app_country] => US
[patent_app_date] => 2013-08-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/962959 | SEMICONDUCTOR PROCESS | Aug 8, 2013 | Abandoned |
Array
(
[id] => 10652176
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[patent_issue_date] => 2016-06-14
[patent_title] => 'Embedded coaxial wire and method of manufacture'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/956176 | Embedded coaxial wire and method of manufacture | Jul 30, 2013 | Issued |
Array
(
[id] => 10974882
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/954453 | Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer | Jul 29, 2013 | Issued |
Array
(
[id] => 10645583
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/937976 | OPTICAL DEVICE AND PROCESSING METHOD OF THE SAME | Jul 8, 2013 | Abandoned |
Array
(
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Array
(
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[patent_title] => 'Trench Liner Passivation for Dark Current Improvement'
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/927698 | Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide | Jun 25, 2013 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/925984 | Deep trench capacitor | Jun 24, 2013 | Issued |