Search

Vincent Wall

Examiner (ID: 17077, Phone: (571)272-9567 , Office: P/2893 )

Most Active Art Unit
2822
Art Unit(s)
2893, 2822, 2898
Total Applications
914
Issued Applications
516
Pending Applications
121
Abandoned Applications
305

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9895553 [patent_doc_number] => 20150050752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'METHODS FOR CLEANING A WAFER EDGE INCLUDING A NOTCH' [patent_app_type] => utility [patent_app_number] => 13/967160 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1781 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967160 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/967160
METHODS FOR CLEANING A WAFER EDGE INCLUDING A NOTCH Aug 13, 2013 Abandoned
Array ( [id] => 9432920 [patent_doc_number] => 20140110826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'BACKSIDE PROTECTION FOR A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP)' [patent_app_type] => utility [patent_app_number] => 13/966506 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2378 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966506 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966506
BACKSIDE PROTECTION FOR A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) Aug 13, 2013 Abandoned
Array ( [id] => 9895592 [patent_doc_number] => 20150050792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'EXTRA NARROW DIFFUSION BREAK FOR 3D FINFET TECHNOLOGIES' [patent_app_type] => utility [patent_app_number] => 13/965258 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2640 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965258 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965258
EXTRA NARROW DIFFUSION BREAK FOR 3D FINFET TECHNOLOGIES Aug 12, 2013 Abandoned
Array ( [id] => 9895552 [patent_doc_number] => 20150050751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'METHOD OF CONTROLLING THRESHOLD VOLTAGE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/965600 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4141 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965600 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965600
Method of controlling threshold voltage and method of fabricating semiconductor device Aug 12, 2013 Issued
Array ( [id] => 9864851 [patent_doc_number] => 20150044870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A SELF-ALIGNED OPL REPLACEMENT CONTACT AND PATTERNED HSQ AND A SEMICONDUCTOR DEVICE FORMED BY SAME' [patent_app_type] => utility [patent_app_number] => 13/964286 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4034 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/964286
Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ and a semiconductor device formed by same Aug 11, 2013 Issued
Array ( [id] => 10395160 [patent_doc_number] => 20150280167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'PACKAGING COVER PLATE FOR ORGANIC LIGHT-EMITTING DEVICE, ORGANIC LIGHT-EMITTING DEVICE AND DISPLAY DEVICE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/236303 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14236303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/236303
PACKAGING COVER PLATE FOR ORGANIC LIGHT-EMITTING DEVICE, ORGANIC LIGHT-EMITTING DEVICE AND DISPLAY DEVICE HAVING THE SAME Aug 11, 2013 Abandoned
Array ( [id] => 9864823 [patent_doc_number] => 20150044842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'Integrating Junction Formation of Transistors with Contact Formation' [patent_app_type] => utility [patent_app_number] => 13/963911 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963911 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/963911
Integrating junction formation of transistors with contact formation Aug 8, 2013 Issued
Array ( [id] => 9785806 [patent_doc_number] => 20140302626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'METHOD OF MANUFACTURING DISPLAY AND DEPOSITION APPARATUS FOR THE SAME' [patent_app_type] => utility [patent_app_number] => 13/964020 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964020 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/964020
METHOD OF MANUFACTURING DISPLAY AND DEPOSITION APPARATUS FOR THE SAME Aug 8, 2013 Abandoned
Array ( [id] => 11221850 [patent_doc_number] => 09450199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Method of forming nano crystals and method of manufacturing organic light-emitting display apparatus including thin film having the same' [patent_app_type] => utility [patent_app_number] => 13/963662 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4019 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/963662
Method of forming nano crystals and method of manufacturing organic light-emitting display apparatus including thin film having the same Aug 8, 2013 Issued
Array ( [id] => 9864812 [patent_doc_number] => 20150044831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'SEMICONDUCTOR PROCESS' [patent_app_type] => utility [patent_app_number] => 13/962959 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13962959 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/962959
SEMICONDUCTOR PROCESS Aug 8, 2013 Abandoned
Array ( [id] => 10652176 [patent_doc_number] => 09368440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-14 [patent_title] => 'Embedded coaxial wire and method of manufacture' [patent_app_type] => utility [patent_app_number] => 13/956176 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5467 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956176 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/956176
Embedded coaxial wire and method of manufacture Jul 30, 2013 Issued
Array ( [id] => 10974882 [patent_doc_number] => 20140377917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN FORMED ON BULK AND GATE CHANNEL FORMED ON OXIDE LAYER' [patent_app_type] => utility [patent_app_number] => 13/954453 [patent_app_country] => US [patent_app_date] => 2013-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 6180 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/954453
Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer Jul 29, 2013 Issued
Array ( [id] => 10645583 [patent_doc_number] => 09362461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Light emitting device and lighting system having the same' [patent_app_type] => utility [patent_app_number] => 13/938469 [patent_app_country] => US [patent_app_date] => 2013-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 13583 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13938469 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/938469
Light emitting device and lighting system having the same Jul 9, 2013 Issued
Array ( [id] => 10652196 [patent_doc_number] => 09368460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Fan-out interconnect structure and method for forming same' [patent_app_type] => utility [patent_app_number] => 13/937726 [patent_app_country] => US [patent_app_date] => 2013-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 4308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13937726 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/937726
Fan-out interconnect structure and method for forming same Jul 8, 2013 Issued
Array ( [id] => 9220201 [patent_doc_number] => 20140014976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'OPTICAL DEVICE AND PROCESSING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 13/937976 [patent_app_country] => US [patent_app_date] => 2013-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4645 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13937976 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/937976
OPTICAL DEVICE AND PROCESSING METHOD OF THE SAME Jul 8, 2013 Abandoned
Array ( [id] => 9696981 [patent_doc_number] => 20140246666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/935195 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11886 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935195 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935195
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Jul 2, 2013 Abandoned
Array ( [id] => 9789725 [patent_doc_number] => 20150001669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'Trench Liner Passivation for Dark Current Improvement' [patent_app_type] => utility [patent_app_number] => 13/930189 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13930189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/930189
Trench liner passivation for dark current improvement Jun 27, 2013 Issued
Array ( [id] => 9258883 [patent_doc_number] => 20130340812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'HIGH VOLTAGE SEMICONDUCTOR BASED WAFER AND A SOLAR MODULE HAVING INTEGRATED ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 13/928567 [patent_app_country] => US [patent_app_date] => 2013-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13245 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13928567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/928567
HIGH VOLTAGE SEMICONDUCTOR BASED WAFER AND A SOLAR MODULE HAVING INTEGRATED ELECTRONIC DEVICES Jun 26, 2013 Abandoned
Array ( [id] => 9789647 [patent_doc_number] => 20150001591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'BULK FINFET WITH PARTIAL DIELECTRIC ISOLATION FEATURING A PUNCH-THROUGH STOPPING LAYER UNDER THE OXIDE' [patent_app_type] => utility [patent_app_number] => 13/927698 [patent_app_country] => US [patent_app_date] => 2013-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13927698 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/927698
Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide Jun 25, 2013 Issued
Array ( [id] => 10971845 [patent_doc_number] => 20140374880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'DEEP TRENCH CAPACITOR' [patent_app_type] => utility [patent_app_number] => 13/925984 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925984 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925984
Deep trench capacitor Jun 24, 2013 Issued
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