
Vincent Wall
Examiner (ID: 5266, Phone: (571)272-9567 , Office: P/2893 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2898, 2893, 2822 |
| Total Applications | 875 |
| Issued Applications | 495 |
| Pending Applications | 124 |
| Abandoned Applications | 302 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17660888
[patent_doc_number] => 20220181353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/530014
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13356
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530014
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/530014 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF | Nov 17, 2021 | Abandoned |
Array
(
[id] => 18113188
[patent_doc_number] => 20230006068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => VERTICAL TRANSISTOR STRUCTURES AND METHODS UTILIZING DEPOSITED MATERIALS
[patent_app_type] => utility
[patent_app_number] => 17/529211
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8441
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529211
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529211 | VERTICAL TRANSISTOR STRUCTURES AND METHODS UTILIZING DEPOSITED MATERIALS | Nov 16, 2021 | Abandoned |
Array
(
[id] => 18113188
[patent_doc_number] => 20230006068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => VERTICAL TRANSISTOR STRUCTURES AND METHODS UTILIZING DEPOSITED MATERIALS
[patent_app_type] => utility
[patent_app_number] => 17/529211
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8441
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529211
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529211 | VERTICAL TRANSISTOR STRUCTURES AND METHODS UTILIZING DEPOSITED MATERIALS | Nov 16, 2021 | Abandoned |
Array
(
[id] => 18125264
[patent_doc_number] => 20230010879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-12
[patent_title] => VERTICAL TRANSISTOR STRUCTURES AND METHODS UTILIZING SELECTIVE FORMATION
[patent_app_type] => utility
[patent_app_number] => 17/529051
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9783
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529051
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529051 | Vertical transistor structures and methods utilizing selective formation | Nov 16, 2021 | Issued |
Array
(
[id] => 19627228
[patent_doc_number] => 12166079
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-10
[patent_title] => 2D channel transistors with low contact resistance
[patent_app_type] => utility
[patent_app_number] => 17/455146
[patent_app_country] => US
[patent_app_date] => 2021-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 35
[patent_no_of_words] => 7364
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455146
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/455146 | 2D channel transistors with low contact resistance | Nov 15, 2021 | Issued |
Array
(
[id] => 18849117
[patent_doc_number] => 20230411521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => TRANSISTOR AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/036727
[patent_app_country] => US
[patent_app_date] => 2021-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25938
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18036727
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/036727 | TRANSISTOR AND SEMICONDUCTOR DEVICE | Nov 8, 2021 | Pending |
Array
(
[id] => 17583249
[patent_doc_number] => 20220140104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/515969
[patent_app_country] => US
[patent_app_date] => 2021-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8792
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515969
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/515969 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME | Oct 31, 2021 | Abandoned |
Array
(
[id] => 17883847
[patent_doc_number] => 20220299324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => ACCIDENT FAULT DETECTION BASED ON MULTIPLE SENSOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/516056
[patent_app_country] => US
[patent_app_date] => 2021-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10048
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516056
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/516056 | ACCIDENT FAULT DETECTION BASED ON MULTIPLE SENSOR DEVICES | Oct 31, 2021 | Pending |
Array
(
[id] => 19844125
[patent_doc_number] => 12256541
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Apparatus and method including memory device having 2-transistor vertical memory cell
[patent_app_type] => utility
[patent_app_number] => 17/515024
[patent_app_country] => US
[patent_app_date] => 2021-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 27
[patent_no_of_words] => 16537
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515024
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/515024 | Apparatus and method including memory device having 2-transistor vertical memory cell | Oct 28, 2021 | Issued |
Array
(
[id] => 17389680
[patent_doc_number] => 20220037532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-03
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/504923
[patent_app_country] => US
[patent_app_date] => 2021-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 61237
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504923
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/504923 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME | Oct 18, 2021 | Abandoned |
Array
(
[id] => 17373970
[patent_doc_number] => 20220029022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => SEMICONDUCTOR FILM
[patent_app_type] => utility
[patent_app_number] => 17/450706
[patent_app_country] => US
[patent_app_date] => 2021-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11809
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450706
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/450706 | SEMICONDUCTOR FILM | Oct 12, 2021 | Pending |
Array
(
[id] => 17373970
[patent_doc_number] => 20220029022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => SEMICONDUCTOR FILM
[patent_app_type] => utility
[patent_app_number] => 17/450706
[patent_app_country] => US
[patent_app_date] => 2021-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11809
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450706
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/450706 | SEMICONDUCTOR FILM | Oct 12, 2021 | Pending |
Array
(
[id] => 17373648
[patent_doc_number] => 20220028700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => GALLIUM OXIDE SUBSTRATE AND METHOD OF MANUFACTURING GALLIUM OXIDE SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/493082
[patent_app_country] => US
[patent_app_date] => 2021-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8119
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493082
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/493082 | GALLIUM OXIDE SUBSTRATE AND METHOD OF MANUFACTURING GALLIUM OXIDE SUBSTRATE | Oct 3, 2021 | Abandoned |
Array
(
[id] => 19720406
[patent_doc_number] => 12205951
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-21
[patent_title] => Complementary metal oxide semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/491841
[patent_app_country] => US
[patent_app_date] => 2021-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7800
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 340
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491841
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/491841 | Complementary metal oxide semiconductor device | Sep 30, 2021 | Issued |
Array
(
[id] => 18670080
[patent_doc_number] => 11776992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => Trench capacitor having improved capacitance and fabrication method thereof
[patent_app_type] => utility
[patent_app_number] => 17/489796
[patent_app_country] => US
[patent_app_date] => 2021-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5597
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489796
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/489796 | Trench capacitor having improved capacitance and fabrication method thereof | Sep 29, 2021 | Issued |
Array
(
[id] => 18024576
[patent_doc_number] => 20220376075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => ACCESS TRANSISTOR INCLUDING A METAL OXIDE BARRIER LAYER AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/485848
[patent_app_country] => US
[patent_app_date] => 2021-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485848
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485848 | ACCESS TRANSISTOR INCLUDING A METAL OXIDE BARRIER LAYER AND METHODS FOR FORMING THE SAME | Sep 26, 2021 | Pending |
Array
(
[id] => 18024576
[patent_doc_number] => 20220376075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => ACCESS TRANSISTOR INCLUDING A METAL OXIDE BARRIER LAYER AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/485848
[patent_app_country] => US
[patent_app_date] => 2021-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485848
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485848 | ACCESS TRANSISTOR INCLUDING A METAL OXIDE BARRIER LAYER AND METHODS FOR FORMING THE SAME | Sep 26, 2021 | Pending |
Array
(
[id] => 20119569
[patent_doc_number] => 12369307
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Access transistors in a dual gate line configuration and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/483900
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 77
[patent_no_of_words] => 10572
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483900
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/483900 | Access transistors in a dual gate line configuration and methods for forming the same | Sep 23, 2021 | Issued |
Array
(
[id] => 18267557
[patent_doc_number] => 20230088799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => METAL-INSULATOR-METAL CAPACITOR STRUCTURE SUPPORTING DIFFERENT VOLTAGE APPLICATIONS
[patent_app_type] => utility
[patent_app_number] => 17/482565
[patent_app_country] => US
[patent_app_date] => 2021-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6240
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482565
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/482565 | Metal-insulator-metal capacitor structure supporting different voltage applications | Sep 22, 2021 | Issued |
Array
(
[id] => 17986342
[patent_doc_number] => 20220352379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => FERROELECTRIC MEMORY DEVICES HAVING IMPROVED FERROELECTRIC PROPERTIES AND METHODS OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/481470
[patent_app_country] => US
[patent_app_date] => 2021-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16775
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481470
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/481470 | FERROELECTRIC MEMORY DEVICES HAVING IMPROVED FERROELECTRIC PROPERTIES AND METHODS OF MAKING THE SAME | Sep 21, 2021 | Pending |