Vincent Wen-liang Chang
Examiner (ID: 11575, Phone: (571)270-1214 , Office: P/2116 )
Most Active Art Unit | 2119 |
Art Unit(s) | 2119, 2115, 2116, 2127 |
Total Applications | 435 |
Issued Applications | 296 |
Pending Applications | 44 |
Abandoned Applications | 95 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5093003
[patent_doc_number] => 20070114612
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-24
[patent_title] => 'Method of fabricating semiconductor devices having MCFET/finFET and related device'
[patent_app_type] => utility
[patent_app_number] => 11/443816
[patent_app_country] => US
[patent_app_date] => 2006-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6860
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0114/20070114612.pdf
[firstpage_image] =>[orig_patent_app_number] => 11443816
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/443816 | Method of fabricating semiconductor devices having MCFET/finFET and related device | May 30, 2006 | Abandoned |
Array
(
[id] => 5683047
[patent_doc_number] => 20060199317
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'THIN FILM TRANSISTOR AND METHOD FOR PRODUCTION THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/420302
[patent_app_country] => US
[patent_app_date] => 2006-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0199/20060199317.pdf
[firstpage_image] =>[orig_patent_app_number] => 11420302
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420302 | THIN FILM TRANSISTOR AND METHOD FOR PRODUCTION THEREOF | May 24, 2006 | Abandoned |
Array
(
[id] => 5222953
[patent_doc_number] => 20070252219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-01
[patent_title] => 'Memory cell array with low resistance common source and high current drivability'
[patent_app_type] => utility
[patent_app_number] => 11/412574
[patent_app_country] => US
[patent_app_date] => 2006-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 5665
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20070252219.pdf
[firstpage_image] =>[orig_patent_app_number] => 11412574
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/412574 | Memory cell array with low resistance common source and high current drivability | Apr 26, 2006 | Issued |
Array
(
[id] => 5683071
[patent_doc_number] => 20060199341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'Methods of forming threshold voltage implant regions'
[patent_app_type] => utility
[patent_app_number] => 11/406893
[patent_app_country] => US
[patent_app_date] => 2006-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6373
[patent_no_of_claims] => 9
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[firstpage_image] =>[orig_patent_app_number] => 11406893
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/406893 | Methods of forming threshold voltage implant regions | Apr 17, 2006 | Issued |
Array
(
[id] => 196579
[patent_doc_number] => 07638392
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-29
[patent_title] => 'Methods of forming capacitor structures'
[patent_app_type] => utility
[patent_app_number] => 11/406862
[patent_app_country] => US
[patent_app_date] => 2006-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 6416
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[pdf_file] => patents/07/638/07638392.pdf
[firstpage_image] =>[orig_patent_app_number] => 11406862
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/406862 | Methods of forming capacitor structures | Apr 17, 2006 | Issued |
Array
(
[id] => 5683070
[patent_doc_number] => 20060199340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'Methods of implanting dopant into channel regions'
[patent_app_type] => utility
[patent_app_number] => 11/406863
[patent_app_country] => US
[patent_app_date] => 2006-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => publications/A1/0199/20060199340.pdf
[firstpage_image] =>[orig_patent_app_number] => 11406863
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/406863 | Methods of implanting dopant into channel regions | Apr 17, 2006 | Issued |
Array
(
[id] => 5649163
[patent_doc_number] => 20060134898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'Semiconductor damascene trench and methods thereof'
[patent_app_type] => utility
[patent_app_number] => 11/348149
[patent_app_country] => US
[patent_app_date] => 2006-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 5750
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20060134898.pdf
[firstpage_image] =>[orig_patent_app_number] => 11348149
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/348149 | Semiconductor damascene trench and methods thereof | Feb 5, 2006 | Abandoned |
Array
(
[id] => 5694235
[patent_doc_number] => 20060154382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-13
[patent_title] => 'Capacitor with high dielectric constant materials and method of making'
[patent_app_type] => utility
[patent_app_number] => 11/346676
[patent_app_country] => US
[patent_app_date] => 2006-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3962
[patent_no_of_claims] => 59
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11346676
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/346676 | Capacitor with high dielectric constant materials and method of making | Feb 2, 2006 | Abandoned |
Array
(
[id] => 5913097
[patent_doc_number] => 20060128159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Method of removing etch residues'
[patent_app_type] => utility
[patent_app_number] => 11/347445
[patent_app_country] => US
[patent_app_date] => 2006-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0128/20060128159.pdf
[firstpage_image] =>[orig_patent_app_number] => 11347445
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/347445 | Method of removing etch residues | Feb 1, 2006 | Abandoned |
Array
(
[id] => 4968636
[patent_doc_number] => 20070108638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-17
[patent_title] => 'ALIGNMENT MARK WITH IMPROVED RESISTANCE TO DICING INDUCED CRACKING AND DELAMINATION IN THE SCRIBE REGION'
[patent_app_type] => utility
[patent_app_number] => 11/164266
[patent_app_country] => US
[patent_app_date] => 2005-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3027
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20070108638.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164266
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164266 | ALIGNMENT MARK WITH IMPROVED RESISTANCE TO DICING INDUCED CRACKING AND DELAMINATION IN THE SCRIBE REGION | Nov 15, 2005 | Abandoned |
Array
(
[id] => 5670334
[patent_doc_number] => 20060175688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-10
[patent_title] => 'STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 11/163556
[patent_app_country] => US
[patent_app_date] => 2005-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3995
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[pdf_file] => publications/A1/0175/20060175688.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163556
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163556 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM | Oct 21, 2005 | Abandoned |
Array
(
[id] => 92006
[patent_doc_number] => 07737003
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-15
[patent_title] => 'Method and structure for optimizing yield of 3-D chip manufacture'
[patent_app_type] => utility
[patent_app_number] => 11/163226
[patent_app_country] => US
[patent_app_date] => 2005-10-11
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[pdf_file] => patents/07/737/07737003.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163226
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163226 | Method and structure for optimizing yield of 3-D chip manufacture | Oct 10, 2005 | Issued |
Array
(
[id] => 5168871
[patent_doc_number] => 20070069302
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-29
[patent_title] => 'Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby'
[patent_app_type] => utility
[patent_app_number] => 11/238445
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[firstpage_image] =>[orig_patent_app_number] => 11238445
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/238445 | Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby | Sep 27, 2005 | Abandoned |
Array
(
[id] => 9762227
[patent_doc_number] => 08846549
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-30
[patent_title] => 'Method of forming bottom oxide for nitride flash memory'
[patent_app_type] => utility
[patent_app_number] => 11/235786
[patent_app_country] => US
[patent_app_date] => 2005-09-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/235786 | Method of forming bottom oxide for nitride flash memory | Sep 26, 2005 | Issued |
Array
(
[id] => 4974108
[patent_doc_number] => 20070215337
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'Heat Sink Material, Manufacturing Method For The Same, And Semiconductor Laser Device'
[patent_app_type] => utility
[patent_app_number] => 11/587036
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[firstpage_image] =>[orig_patent_app_number] => 11587036
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/587036 | Heat Sink Material, Manufacturing Method For The Same, And Semiconductor Laser Device | Sep 19, 2005 | Abandoned |
Array
(
[id] => 5894993
[patent_doc_number] => 20060003532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-05
[patent_title] => 'Semiconductor device and method of manufacturing therefor'
[patent_app_type] => utility
[patent_app_number] => 11/221823
[patent_app_country] => US
[patent_app_date] => 2005-09-09
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[pdf_file] => publications/A1/0003/20060003532.pdf
[firstpage_image] =>[orig_patent_app_number] => 11221823
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/221823 | Semiconductor device and method of manufacturing therefor | Sep 8, 2005 | Abandoned |
Array
(
[id] => 5757338
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[patent_title] => 'Semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/217295 | Semiconductor device | Sep 1, 2005 | Abandoned |
Array
(
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[patent_title] => 'Interconnection structure used in a pad region of a semiconductor substrate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/218456 | Interconnection structure used in a pad region of a semiconductor substrate | Sep 1, 2005 | Issued |
Array
(
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[patent_issue_date] => 2005-12-29
[patent_title] => 'Methods for forming openings in doped silicon dioxide'
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[firstpage_image] =>[orig_patent_app_number] => 11214225
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/214225 | Methods for forming openings in doped silicon dioxide | Aug 28, 2005 | Abandoned |
Array
(
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[patent_issue_date] => 2014-08-05
[patent_title] => 'Land grid array semiconductor device packages'
[patent_app_type] => utility
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11212215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/212215 | Land grid array semiconductor device packages | Aug 24, 2005 | Issued |