Search

Vincent Wen-liang Chang

Examiner (ID: 11575, Phone: (571)270-1214 , Office: P/2116 )

Most Active Art Unit
2119
Art Unit(s)
2119, 2115, 2116, 2127
Total Applications
435
Issued Applications
296
Pending Applications
44
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5838297 [patent_doc_number] => 20060118955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Robust copper interconnection structure and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/002256 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4162 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118955.pdf [firstpage_image] =>[orig_patent_app_number] => 11002256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002256
Robust copper interconnection structure and fabrication method thereof Dec 2, 2004 Abandoned
Array ( [id] => 151442 [patent_doc_number] => 07682952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Method for forming low defect density alloy graded layers and structure containing such layers' [patent_app_type] => utility [patent_app_number] => 10/999486 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 8171 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/682/07682952.pdf [firstpage_image] =>[orig_patent_app_number] => 10999486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999486
Method for forming low defect density alloy graded layers and structure containing such layers Nov 29, 2004 Issued
Array ( [id] => 7214024 [patent_doc_number] => 20050253189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices having recessed channels and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/999306 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4387 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20050253189.pdf [firstpage_image] =>[orig_patent_app_number] => 10999306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999306
Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices having recessed channels Nov 29, 2004 Issued
Array ( [id] => 5611705 [patent_doc_number] => 20060113631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Structure of embedded capacitors and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 10/998076 [patent_app_country] => US [patent_app_date] => 2004-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1305 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20060113631.pdf [firstpage_image] =>[orig_patent_app_number] => 10998076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998076
Structure of embedded capacitors and fabrication method thereof Nov 25, 2004 Abandoned
Array ( [id] => 558957 [patent_doc_number] => 07468539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-23 [patent_title] => 'Field-effect transistor with a gate having a plurality of branching elements arranged parallel to each other' [patent_app_type] => utility [patent_app_number] => 10/982916 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 12399 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/468/07468539.pdf [firstpage_image] =>[orig_patent_app_number] => 10982916 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982916
Field-effect transistor with a gate having a plurality of branching elements arranged parallel to each other Nov 7, 2004 Issued
Array ( [id] => 270491 [patent_doc_number] => 07563727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Low-k dielectric layer formed from aluminosilicate precursors' [patent_app_type] => utility [patent_app_number] => 10/984595 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4156 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563727.pdf [firstpage_image] =>[orig_patent_app_number] => 10984595 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/984595
Low-k dielectric layer formed from aluminosilicate precursors Nov 7, 2004 Issued
Array ( [id] => 5741265 [patent_doc_number] => 20060086987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Method for manufacturing a semiconductor device with reduced floating body effect' [patent_app_type] => utility [patent_app_number] => 10/973966 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 3615 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20060086987.pdf [firstpage_image] =>[orig_patent_app_number] => 10973966 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973966
Method for manufacturing a semiconductor device with reduced floating body effect Oct 25, 2004 Issued
Array ( [id] => 7198597 [patent_doc_number] => 20050051850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/967265 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7234 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051850.pdf [firstpage_image] =>[orig_patent_app_number] => 10967265 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/967265
Semiconductor device and method of manufacturing the same Oct 18, 2004 Abandoned
Array ( [id] => 7080634 [patent_doc_number] => 20050046014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Isolating temperature sensitive components from heat sources in integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/964386 [patent_app_country] => US [patent_app_date] => 2004-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 688 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20050046014.pdf [firstpage_image] =>[orig_patent_app_number] => 10964386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/964386
Isolating temperature sensitive components from heat sources in integrated circuits Oct 11, 2004 Abandoned
Array ( [id] => 5713241 [patent_doc_number] => 20060076604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Virtual ground memory array and method therefor' [patent_app_type] => utility [patent_app_number] => 10/961296 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2207 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076604.pdf [firstpage_image] =>[orig_patent_app_number] => 10961296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/961296
Virtual ground memory array and method therefor Oct 7, 2004 Abandoned
Array ( [id] => 7154280 [patent_doc_number] => 20050082548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'III-V group GaN-based semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/951905 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3837 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082548.pdf [firstpage_image] =>[orig_patent_app_number] => 10951905 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/951905
III-V group GaN-based semiconductor device and method of manufacturing the same Sep 28, 2004 Abandoned
Array ( [id] => 5718454 [patent_doc_number] => 20060071227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'System and method for active array temperature sensing and cooling' [patent_app_type] => utility [patent_app_number] => 10/950646 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4563 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071227.pdf [firstpage_image] =>[orig_patent_app_number] => 10950646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950646
System and method for active array temperature sensing and cooling Sep 27, 2004 Issued
Array ( [id] => 7191339 [patent_doc_number] => 20050040470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Fabrication of self-aligned bipolar transistor' [patent_app_type] => utility [patent_app_number] => 10/951377 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5557 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20050040470.pdf [firstpage_image] =>[orig_patent_app_number] => 10951377 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/951377
Fabrication of self-aligned bipolar transistor Sep 27, 2004 Abandoned
Array ( [id] => 6971860 [patent_doc_number] => 20050037570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Semiconductor capacitor structure and method to form same' [patent_app_type] => utility [patent_app_number] => 10/949066 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1515 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20050037570.pdf [firstpage_image] =>[orig_patent_app_number] => 10949066 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/949066
Semiconductor capacitor structure and method to form same Sep 23, 2004 Abandoned
Array ( [id] => 7220273 [patent_doc_number] => 20050077553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Methods of forming multi fin FETs using sacrificial fins and devices so formed' [patent_app_type] => utility [patent_app_number] => 10/947505 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077553.pdf [firstpage_image] =>[orig_patent_app_number] => 10947505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/947505
Methods of forming multi fin FETs using sacrificial fins and devices so formed Sep 21, 2004 Abandoned
Array ( [id] => 5823744 [patent_doc_number] => 20060060926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Semiconductor scheme for reduced circuit area in a simplified process' [patent_app_type] => utility [patent_app_number] => 10/944626 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6894 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060926.pdf [firstpage_image] =>[orig_patent_app_number] => 10944626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944626
Semiconductor scheme for reduced circuit area in a simplified process Sep 16, 2004 Issued
Array ( [id] => 7116754 [patent_doc_number] => 20050070055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Thin film transistor and method for production thereof' [patent_app_type] => utility [patent_app_number] => 10/942066 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6405 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070055.pdf [firstpage_image] =>[orig_patent_app_number] => 10942066 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/942066
Thin film transistor and method for production thereof Sep 14, 2004 Abandoned
Array ( [id] => 5879813 [patent_doc_number] => 20060028895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Silver island anti-fuse' [patent_app_type] => utility [patent_app_number] => 10/914255 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5686 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20060028895.pdf [firstpage_image] =>[orig_patent_app_number] => 10914255 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914255
Silver island anti-fuse Aug 8, 2004 Abandoned
Array ( [id] => 5817951 [patent_doc_number] => 20060022264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method of making a double gate semiconductor device with self-aligned gates and structure thereof' [patent_app_type] => utility [patent_app_number] => 10/909095 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4852 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022264.pdf [firstpage_image] =>[orig_patent_app_number] => 10909095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909095
Method of making a double gate semiconductor device with self-aligned gates and structure thereof Jul 29, 2004 Abandoned
Array ( [id] => 7323431 [patent_doc_number] => 20040251511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Semiconductor device including an isolation trench having a dopant barrier layer formed on a sidewall thereof and a method of manufacture therefor' [patent_app_type] => new [patent_app_number] => 10/884726 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3546 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20040251511.pdf [firstpage_image] =>[orig_patent_app_number] => 10884726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884726
Semiconductor device including an isolation trench having a dopant barrier layer formed on a sidewall thereof and a method of manufacture therefor Jul 1, 2004 Abandoned
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