Search

Vinh P Nguyen

Examiner (ID: 15293, Phone: (571)272-1964 , Office: P/2867 )

Most Active Art Unit
2858
Art Unit(s)
2607, 2829, 3621, 2213, 2899, 2867, 2731, 2858
Total Applications
3579
Issued Applications
3061
Pending Applications
115
Abandoned Applications
402

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15906291 [patent_doc_number] => 20200152666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Integrated Circuit Structure and Method with Hybrid Orientation for FinFET [patent_app_type] => utility [patent_app_number] => 16/741530 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741530 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741530
Integrated circuit structure and method with hybrid orientation for FinFET Jan 12, 2020 Issued
Array ( [id] => 17381141 [patent_doc_number] => 11239174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Semiconductor package structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/728789 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9504 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728789
Semiconductor package structure and method for manufacturing the same Dec 26, 2019 Issued
Array ( [id] => 16765507 [patent_doc_number] => 20210111089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES HAVING HYDROGEN BLOCKING LAYER AND FABRICATION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/727870 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727870
Three-dimensional memory devices having hydrogen blocking layer and fabrication methods thereof Dec 25, 2019 Issued
Array ( [id] => 16920699 [patent_doc_number] => 20210193791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => HIGH DIELECTRIC CONSTANT MATERIAL AT LOCATIONS OF HIGH FIELDS [patent_app_type] => utility [patent_app_number] => 16/726477 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726477
High dielectric constant material at locations of high fields Dec 23, 2019 Issued
Array ( [id] => 17431812 [patent_doc_number] => 20220059521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SYSTEM AND METHOD OF FABRICATING DISPLAY STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/417651 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17417651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/417651
SYSTEM AND METHOD OF FABRICATING DISPLAY STRUCTURES Dec 16, 2019 Pending
Array ( [id] => 15775835 [patent_doc_number] => 20200118935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => CONTACT STRUCTURE AND FORMATION THEREOF [patent_app_type] => utility [patent_app_number] => 16/716441 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716441
Contact structure and formation thereof Dec 15, 2019 Issued
Array ( [id] => 15775913 [patent_doc_number] => 20200118974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/714176 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714176 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714176
Semiconductor structure Dec 12, 2019 Issued
Array ( [id] => 18639540 [patent_doc_number] => 11764161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Ground connection for semiconductor device assembly [patent_app_type] => utility [patent_app_number] => 16/706443 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6974 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706443
Ground connection for semiconductor device assembly Dec 5, 2019 Issued
Array ( [id] => 16973823 [patent_doc_number] => 11069805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Embedded JFETs for high voltage applications [patent_app_type] => utility [patent_app_number] => 16/704172 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704172 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704172
Embedded JFETs for high voltage applications Dec 4, 2019 Issued
Array ( [id] => 15745889 [patent_doc_number] => 20200111834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => INTEGRATED PIEZOELECTRIC MICROELECTROMECHANICAL ULTRASOUND TRANSDUCER (PMUT) ON INTEGRATED CIRCUIT (IC) FOR FINGERPRINT SENSING [patent_app_type] => utility [patent_app_number] => 16/698497 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698497
INTEGRATED PIEZOELECTRIC MICROELECTROMECHANICAL ULTRASOUND TRANSDUCER (PMUT) ON INTEGRATED CIRCUIT (IC) FOR FINGERPRINT SENSING Nov 26, 2019 Abandoned
Array ( [id] => 15656907 [patent_doc_number] => 20200090984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => Multi-Patterning to Form Vias with Straight Profiles [patent_app_type] => utility [patent_app_number] => 16/694406 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694406
Multi-patterning to form vias with straight profiles Nov 24, 2019 Issued
Array ( [id] => 17574311 [patent_doc_number] => 11322586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/682299 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5434 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682299 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682299
Semiconductor device Nov 12, 2019 Issued
Array ( [id] => 16759997 [patent_doc_number] => 10978555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Semiconductor structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/681782 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 3924 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681782 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681782
Semiconductor structure and method of forming the same Nov 11, 2019 Issued
Array ( [id] => 17092795 [patent_doc_number] => 11120992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Method of fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 16/679340 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 65 [patent_no_of_words] => 8586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679340 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679340
Method of fabricating semiconductor device Nov 10, 2019 Issued
Array ( [id] => 17045980 [patent_doc_number] => 11099152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Backside CMOS compatible BioFET with no plasma induced damage [patent_app_type] => utility [patent_app_number] => 16/679015 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 5261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679015
Backside CMOS compatible BioFET with no plasma induced damage Nov 7, 2019 Issued
Array ( [id] => 16765589 [patent_doc_number] => 20210111171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => ELECTROSTATIC DISCHARGE HANDLING FOR SENSE IGBT USING ZENER DIODE [patent_app_type] => utility [patent_app_number] => 16/675875 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675875
Electrostatic discharge handling for sense IGBT using Zener diode Nov 5, 2019 Issued
Array ( [id] => 16812169 [patent_doc_number] => 20210134724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => MULTI-CHIP PACKAGE STRUCTURES FORMED WITH INTERCONNECT BRIDGE DEVICES AND CHIP PACKAGES WITH DISCRETE REDISTRIBUTION LAYERS [patent_app_type] => utility [patent_app_number] => 16/671411 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671411
Multi-chip package structures with discrete redistribution layers Oct 31, 2019 Issued
Array ( [id] => 18131240 [patent_doc_number] => 11557455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Charged particle source module [patent_app_type] => utility [patent_app_number] => 16/600364 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16600364 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/600364
Charged particle source module Oct 10, 2019 Issued
Array ( [id] => 16566842 [patent_doc_number] => 10892218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/597149 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 18542 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597149 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597149
Semiconductor device Oct 8, 2019 Issued
Array ( [id] => 16594346 [patent_doc_number] => 10903625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Manufacturable laser diode formed on c-plane gallium and nitrogen material [patent_app_type] => utility [patent_app_number] => 16/586100 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 47 [patent_no_of_words] => 30776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586100 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586100
Manufacturable laser diode formed on c-plane gallium and nitrogen material Sep 26, 2019 Issued
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