Search

Vinh P Nguyen

Examiner (ID: 15293, Phone: (571)272-1964 , Office: P/2867 )

Most Active Art Unit
2858
Art Unit(s)
2607, 2829, 3621, 2213, 2899, 2867, 2731, 2858
Total Applications
3579
Issued Applications
3061
Pending Applications
115
Abandoned Applications
402

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11990301 [patent_doc_number] => 20170294456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'HYBRID THIN FILM TRANSISTOR STRUCTURE, DISPLAY DEVICE, AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/436073 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 14153 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436073
Hybrid thin film transistor structure, display device, and method of making the same Feb 16, 2017 Issued
Array ( [id] => 11666101 [patent_doc_number] => 20170154820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'FETS AND METHODS OF FORMING FETS' [patent_app_type] => utility [patent_app_number] => 15/432438 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 14581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432438 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432438
FETS and methods of forming FETS Feb 13, 2017 Issued
Array ( [id] => 15200251 [patent_doc_number] => 10497627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Method of manufacturing a dopant transistor located vertically on the gate [patent_app_type] => utility [patent_app_number] => 15/421641 [patent_app_country] => US [patent_app_date] => 2017-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 32 [patent_no_of_words] => 5945 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421641 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/421641
Method of manufacturing a dopant transistor located vertically on the gate Jan 31, 2017 Issued
Array ( [id] => 11839981 [patent_doc_number] => 20170221701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'RTP PROCESS FOR DIRECTED SELF-ALIGNED PATTERNS' [patent_app_type] => utility [patent_app_number] => 15/422116 [patent_app_country] => US [patent_app_date] => 2017-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15422116 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/422116
RTP PROCESS FOR DIRECTED SELF-ALIGNED PATTERNS Jan 31, 2017 Abandoned
Array ( [id] => 17055871 [patent_doc_number] => 20210265305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => ELECTRONIC DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 16/467975 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467975 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/467975
Electronic device package Dec 30, 2016 Issued
Array ( [id] => 13201801 [patent_doc_number] => 10115821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => FDSOI LDMOS semiconductor device [patent_app_type] => utility [patent_app_number] => 15/383592 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383592
FDSOI LDMOS semiconductor device Dec 18, 2016 Issued
Array ( [id] => 12850333 [patent_doc_number] => 20180175284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH MAGNETIC TUNNEL JUNCTION (MTJ) STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/383122 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383122 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383122
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH MAGNETIC TUNNEL JUNCTION (MTJ) STRUCTURES Dec 18, 2016 Abandoned
Array ( [id] => 15376207 [patent_doc_number] => 10529832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Shallow, abrupt and highly activated tin extension implant junction [patent_app_type] => utility [patent_app_number] => 15/383537 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5406 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383537 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383537
Shallow, abrupt and highly activated tin extension implant junction Dec 18, 2016 Issued
Array ( [id] => 12849346 [patent_doc_number] => 20180174955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => MULTI-LAYER STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME AND A CORRESPONDING CONTACT STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/382969 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382969 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/382969
Multi-layer structure and a method for manufacturing the same and a corresponding contact structure Dec 18, 2016 Issued
Array ( [id] => 11911482 [patent_doc_number] => 09780307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method of manufacturing a display device' [patent_app_type] => utility [patent_app_number] => 15/377128 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 4170 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377128 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377128
Method of manufacturing a display device Dec 12, 2016 Issued
Array ( [id] => 12823366 [patent_doc_number] => 20180166294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => APPARATUS AND METHODS TO ACHIEVE UNIFORM PACKAGE THICKNESS [patent_app_type] => utility [patent_app_number] => 15/377635 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377635
APPARATUS AND METHODS TO ACHIEVE UNIFORM PACKAGE THICKNESS Dec 12, 2016 Abandoned
Array ( [id] => 11694295 [patent_doc_number] => 20170170012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'METHOD OF INTERCALATING INSULATING LAYER BETWEEN METAL CATALYST LAYER AND GRAPHENE LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/377237 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2691 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377237 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377237
METHOD OF INTERCALATING INSULATING LAYER BETWEEN METAL CATALYST LAYER AND GRAPHENE LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME Dec 12, 2016 Abandoned
Array ( [id] => 11904240 [patent_doc_number] => 09773680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Advanced method for scaled SRAM with flexible active pitch' [patent_app_type] => utility [patent_app_number] => 15/377503 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 3235 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377503 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377503
Advanced method for scaled SRAM with flexible active pitch Dec 12, 2016 Issued
Array ( [id] => 11997526 [patent_doc_number] => 20170301681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'CONFIGURABLE ROM' [patent_app_type] => utility [patent_app_number] => 15/377861 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1962 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377861
CONFIGURABLE ROM Dec 12, 2016 Abandoned
Array ( [id] => 13173817 [patent_doc_number] => 10103030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Methods of fabricating semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/377113 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 8762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377113
Methods of fabricating semiconductor devices Dec 12, 2016 Issued
Array ( [id] => 12102021 [patent_doc_number] => 09859120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines' [patent_app_type] => utility [patent_app_number] => 15/377125 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 55 [patent_no_of_words] => 7377 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377125
Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines Dec 12, 2016 Issued
Array ( [id] => 11718255 [patent_doc_number] => 20170186754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'ATOMIC LAYER DEPOSITION OF III-V COMPOUNDS TO FORM V-NAND DEVICES' [patent_app_type] => utility [patent_app_number] => 15/377439 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377439
Atomic layer deposition of III-V compounds to form V-NAND devices Dec 12, 2016 Issued
Array ( [id] => 11694348 [patent_doc_number] => 20170170065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'CARBON FILM FORMING METHOD, CARBON FILM FORMING APPARATUS, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/377141 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5589 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377141 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377141
CARBON FILM FORMING METHOD, CARBON FILM FORMING APPARATUS, AND STORAGE MEDIUM Dec 12, 2016 Abandoned
Array ( [id] => 11732777 [patent_doc_number] => 20170194220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'Preheat Processes for Millisecond Anneal System' [patent_app_type] => utility [patent_app_number] => 15/377121 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377121
Preheat processes for millisecond anneal system Dec 12, 2016 Issued
Array ( [id] => 13667369 [patent_doc_number] => 10163863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Recessed and embedded die coreless package [patent_app_type] => utility [patent_app_number] => 15/375112 [patent_app_country] => US [patent_app_date] => 2016-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2432 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375112 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375112
Recessed and embedded die coreless package Dec 10, 2016 Issued
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